公开(公告)号：US11538508B2

公开(公告)日：2022-12-27

申请号：US17137975

申请日：2020-12-30

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Matthew A. Prather ,  Brent Keeth ,  Frank F Ross ,  Daniel Benjamin Stewart ,  Randall J. Rooney

IPC: G11C7/10 ,  G11C7/22

Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

公开(公告)号：US20220399902A1

公开(公告)日：2022-12-15

申请号：US17348654

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Markus H. Geiger ,  Matthew A. Prather ,  Sujeet Ayyapureddi ,  C. Omar Benitez ,  Dennis Montierth

IPC: H03M13/09 ,  G06F11/10

Abstract: Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.

公开(公告)号：US20220229791A1

公开(公告)日：2022-07-21

申请号：US17712006

申请日：2022-04-01

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Frank F. Ross ,  Randall J. Rooney

IPC: G06F13/16 ,  G11C11/406 ,  G11C7/22 ,  G06F3/06 ,  G06F13/40

Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

公开(公告)号：US20220214600A1

公开(公告)日：2022-07-07

申请号：US17700187

申请日：2022-03-21

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G03B11/04 ,  G03B17/12 ,  H04N5/225 ,  G06V10/147

Abstract: The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.

公开(公告)号：US20220129348A1

公开(公告)日：2022-04-28

申请号：US17571189

申请日：2022-01-07

Applicant: Micron Technology, Inc.

Inventor： Randall J. Rooney ,  Matthew A. Prather

IPC: G06F11/10 ,  G11C11/408 ,  G11C11/406

Abstract: Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.

公开(公告)号：US11301403B2

公开(公告)日：2022-04-12

申请号：US16289967

申请日：2019-03-01

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F13/16 ,  G06F3/06 ,  G11C5/04

Abstract: The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.

公开(公告)号：US20220068778A1

公开(公告)日：2022-03-03

申请号：US17411879

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Scott R. Cyr ,  Stephen F. Moxham ,  Matthew A. Prather ,  Scott Smith

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10

Abstract: Apparatuses, such as semiconductor device packages, may include, for example, a device substrate including a semiconductor material and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.

公开(公告)号：US11126251B2

公开(公告)日：2021-09-21

申请号：US16290181

申请日：2019-03-01

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F1/32 ,  G06F1/3234 ,  G11C5/14 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to power management in memory. Memory devices with multiple input/output ports may have the ports separately managed to transfer data from the various to a host or other components of the module based on certain power management signaling or constraints. For example, a memory device with multiple ports may be managed to transfer data to a host from one set of ports in response to power management (or other) signaling, and the device may be managed to transfer other data to another memory device in response to different power management (or other signaling). Power management may be done onboard a memory module with or without direction from a host. Power management may be performed by a dedicated integrated circuit. Data may be transferred from or between different classes of memory devices, using different ports, based on power management, e.g., criteria.

公开(公告)号：US20210255779A1

公开(公告)日：2021-08-19

申请号：US17313860

申请日：2021-05-06

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F3/06 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to dual speed memory. A memory module can include a number of memory devices that coupled to a host via a number of first ports and coupled to a controller via a number of second ports. The memory module can be configured to transfer data on the first number of ports at a first clock speed and transfer data on the second number of ports at a second clock speed. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports, and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host at a first clock speed via the first number of ports and the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices at a second clock speed via the second number of ports.

公开(公告)号：US20210201970A1

公开(公告)日：2021-07-01

申请号：US17200233

申请日：2021-03-12

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/40 ,  G11C8/10

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.