公开(公告)号：US20140322890A1

公开(公告)日：2014-10-30

申请号：US14323945

申请日：2014-07-03

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha

IPC: H01L21/768 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76882 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.

Abstract translation: 本文公开了用于从微电子衬底去除导电材料（例如贵金属）的抛光系统和方法。 所述方法的若干实施例包括在基底材料中形成孔，将导电材料设置在基底材料和孔中，并将填充材料设置在导电材料上。 填充材料至少部分地填充孔。 然后抛光衬底材料以去除导电材料和孔的外部的填充材料的至少一部分，在此期间，填充材料在抛光衬底材料期间基本上防止导电材料污染到孔中。

公开(公告)号：US08871120B2

公开(公告)日：2014-10-28

申请号：US14046832

申请日：2013-10-04

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha

IPC: H01B1/02 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3081 ,  H01L21/31111

Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.

Abstract translation: 一些实施方案包括去除其中二氧化硅暴露于包括活性氢和至少一种伯，仲，叔或季铵卤化物的混合物的二氧化硅的方法。 混合物还可以包括铊，BX 3和PQ 3中的一种或多种，​​其中X和Q是卤化物。 一些实施方案包括相对于掺杂二氧化硅选择性地蚀刻未掺杂二氧化硅的方法，其中在蚀刻之前将铊掺入掺杂的二氧化硅中。 一些实施方案包括含有掺杂铊的二氧化硅至约1重量％至约10重量％的浓度的物质的组合物。

公开(公告)号：US20140246716A1

公开(公告)日：2014-09-04

申请号：US14274933

申请日：2014-05-12

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/0688 ,  H01L29/78642 ,  H01L29/7889

Abstract: Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.

Abstract translation: 描述制造多层半导体器件的方法以及包括它们的装置和系统。 在一种这样的方法中，形成第一电介质，并且形成与第一电介质接触的第二电介质。 通过第一电介质和第二电介质通过第一蚀刻化学品形成通道，在第一电介质中用第二蚀刻化学物质形成空隙，并且器件至少部分地形成在第一电介质的空隙中。 还描述了另外的实施例。

公开(公告)号：US20140004256A1

公开(公告)日：2014-01-02

申请号：US14019298

申请日：2013-09-05

Applicant: Micron Technology, Inc.

Inventor： Nishant Sinha

IPC: H01L21/28

CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L21/02068 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/316 ,  H01L29/7881

Abstract: Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to form a dispersion, forming an aerosol from the dispersion, and then directing the aerosol onto a substrate to form charge-trapping centers comprising the nanoparticles. The charge-trapping zones may be incorporated into flash memory cells.

Abstract translation: 一些实施方案包括形成电荷捕获区的方法。 所述方法可以包括形成纳米颗粒，将纳米颗粒转移到液体中以形成分散体，从分散体形成气溶胶，然后将气溶胶引导到基底上以形成包含纳米颗粒的电荷捕获中心。 电荷捕获区域可以并入闪存单元中。

公开(公告)号：US20130320291A1

公开(公告)日：2013-12-05

申请号：US13961479

申请日：2013-08-07

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC: H01L45/00

CPC classification number: H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

Abstract translation: 形成用于半导体结构和存储单元的导电元件例如互连和电极的方法。 所述方法包括在至少一个开口的一部分中形成第一导电材料和第二导电材料，所述第二导电材料包括银，并且执行抛光工艺以用至少一个第一和第二导电材料填充所述至少一个开口。 可以进行退火处理以形成银和第一导电材料的混合物或合金。 该方法能够形成具有减小的尺寸（例如，小于约20nm）的含银导电元件。 所得的导电元件具有所需的电阻率。 所述方法可以用于例如形成用于电连接有源器件并形成用于存储器单元的电极的互连。 还公开了一种半导体结构和包括这种导电结构的存储单元。