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公开(公告)号：US11556261B2
公开(公告)日：2023-01-17
申请号：US16994213
申请日：2020-08-14
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Chun Sum Yeung , Xiangang Luo
Abstract: A method includes writing, to a first sub-set of memory blocks of a first plane associated with a memory device, first data corresponding to recovery of an uncorrectable error and writing, to a first sub-set of memory blocks of a second memory plane associated with the memory device, second data corresponding to recovery of the uncorrectable error. A relative physical location of the first sub-set of memory blocks of the first memory plane and a relative physical location of the first sub-set of memory blocks of the second memory plane are a same relative physical location with respect to the first memory plane and the second memory plane.
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公开(公告)号：US11522559B2
公开(公告)日：2022-12-06
申请号：US17181712
申请日：2021-02-22
Applicant: Micron Technology, Inc.
Inventor： Xiangang Luo , Ting Luo
Abstract: Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.
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公开(公告)号：US20220351762A1
公开(公告)日：2022-11-03
申请号：US17718617
申请日：2022-04-12
Applicant: Micron Technology, Inc.
Inventor： Cheng Cheng Ang , Chun Lei Kong , Ting Luo , Aik Boon Edmund Yap
Abstract: Methods, systems, and devices for skipping pages for weak wordlines of a memory device during pre-programming are described. A memory device may be configured to operate in a first mode involving skipping one or more pages (e.g., a lower page (LP)) associated with a set of wordlines. In some examples, a testing system may determine the set of wordlines (e.g., weak wordlines) for which to skip pages according to performance degradation for the wordlines in response to applying a threshold temperature to a test memory device. In the first mode, the memory device may store (e.g., pre-program) data in a subset of pages distinct from the skipped pages. The memory device may switch to a second mode in response to a trigger condition. In the second mode, the memory device may use each page associated with the wordlines and may refrain from skipping the one or more pages.
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公开(公告)号：US20220350521A1
公开(公告)日：2022-11-03
申请号：US17244290
申请日：2021-04-29
Applicant: Micron Technology, Inc.
Inventor： Tao Liu , Ting Luo , Jianmin Huang
IPC: G06F3/06
Abstract: A method includes determining a first memory access count threshold for a first word line of a block of memory cells and determining a second memory access count threshold for a second word line of the block of memory cells. The second memory access count threshold can be greater than the first memory access count threshold. The method can further include incrementing a memory block access count corresponding to the block of memory cells that includes the first word line and the second word line in response to receiving a memory access command and refreshing the first word line when the memory block access count corresponding to the block of memory cells is equal to the first memory access count threshold.
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公开(公告)号：US20220334753A1
公开(公告)日：2022-10-20
申请号：US17234095
申请日：2021-04-19
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yueng , Guang Hu , Ting Luo , Tao Liu
IPC: G06F3/06
Abstract: A method includes performing a first read operation involving a set of memory cells using a first voltage, determining a quantity of bits associated with the set of memory cells based on the first read operation, performing a second read operation involving the set of memory cells using a second voltage that is greater than the first voltage when the quantity of bits is above a threshold quantity of bits for the set of memory cells, and performing the second read operation involving the set of memory cells using a third voltage that is less than the first voltage when the quantity of bits is below the threshold quantity of bits for the set of memory cells.
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Patent Agency Ranking
公开(公告)号：US11442833B2
公开(公告)日：2022-09-13
申请号：US17085671
申请日：2020-10-30
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Tao Liu , Christopher J. Bueb , Eric Yuen , Cheng Cheng Ang
IPC: G06F11/00 , G06F11/30 , G06F11/07 , G11C7/04 , G11C11/406
Abstract: A method includes monitoring a temperature of a memory component of a memory sub-system to determine that the temperature of the memory component corresponds to a first monitored temperature value; writing data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the first monitored temperature value; determining that the first monitored temperature value exceeds a threshold temperature range; monitoring the temperature of the memory component of the memory sub-system to determine that the temperature of the memory component corresponds to a second monitored temperature value that is within the threshold temperature range; and rewriting the data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the second monitored temperature value.
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公开(公告)号：US11335429B1
公开(公告)日：2022-05-17
申请号：US17122864
申请日：2020-12-15
Applicant: Micron Technology, Inc.
Inventor： Guang Hu , Ting Luo , Chun Sum Yueng
Abstract: A method includes determining whether a data reliability parameter associated with a set of memory cells is greater than a threshold data reliability parameter and in response to determining that the data reliability parameter is greater than the threshold data reliability parameter, performing an error recovery operation. The method further includes, subsequent to performing the error recovery operation, determining whether the data reliability parameter associated with the set of memory cells is less than the threshold data reliability parameter and in response to determining that the data reliability parameter is less than the threshold data reliability parameter, setting an offset associated with the error recovery operation as a default read voltage for the set of memory cells.
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公开(公告)号：US20220138043A1
公开(公告)日：2022-05-05
申请号：US17087334
申请日：2020-11-02
Applicant: Micron Technology, Inc.
Abstract: An apparatus includes a memory sub-system comprising a plurality of memory blocks and a memory block defect detection component. The memory block defect detection component is to set, for a memory block among the plurality of memory blocks, a first block defect detection rate and determine whether the first block defect detection rate is greater than a threshold block defect detection rate for the at least one memory block. In response to a determination that the first block defect detection rate is greater than the threshold block defect detection rate for the memory block, the memory block defect detection component is to assert a program command on the memory block determine whether a program operation associated with assertion of the program command on the at least one memory block is successful. In response to a determination the program operation is unsuccessful, the memory block defect detection component is to determine that a failure involving a plane associated with the memory block and another plane of the memory sub-system has occurred.
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公开(公告)号：US20210390014A1
公开(公告)日：2021-12-16
申请号：US17458224
申请日：2021-08-26
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Falgun G. Trivedi , Harish Reddy Singidi , Xiangang Luo , Preston Allen Thomson , Ting Luo , Jianmin Huang
IPC: G06F11/10 , G06F12/0882 , G06F11/07 , G06F12/02
Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US20210257031A1
公开(公告)日：2021-08-19
申请号：US17313249
申请日：2021-05-06
Applicant: Micron Technology, Inc.
Inventor： Ashutosh Malshe , Kishore Kumar Muchherla , Harish Reddy Singidi , Peter Sean Feeley , Sampath Ratnam , Kulachet Tanpairoj , Ting Luo
Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
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