公开(公告)号：US20140082440A1

公开(公告)日：2014-03-20

申请号：US13866834

申请日：2013-04-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kin-Chu Ho ,  Hsiang-Pang Li ,  Hsie-Chia Chang

IPC: G11C29/50

CPC classification number: G11C29/50004 ,  G06F11/1048 ,  G11C11/5642 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42

Abstract: Multiple measurements are made with one memory sense operation having a first word line sensing voltage on a memory cell. The multiple measurements include a first measurement, of whether the memory cell stores either: (a) data corresponding to a first set of one or more threshold voltage ranges below the first word line sensing voltage of the one memory sense operation, or (b) data corresponding to a second set of one or more threshold voltage ranges above the first word line sensing voltage of the one memory sense operation. The multiple measurements include a second measurement, of error correction data of the memory cell indicating relative position within a particular threshold voltage range of a stored threshold voltage in the memory cell.

Abstract translation: 通过在存储器单元上具有第一字线感测电压的一个存储器感测操作进行多次测量。 多个测量包括第一测量，存储单元是否存储：（a）与一个存储器感测操作的第一字线感测电压之下的一个或多个阈值电压范围的第一组对应的数据，或（b） 数据对应于在一个存储器感测操作的第一字线感测电压之上的一个或多个阈值电压范围的第二组。 所述多个测量包括第二测量，所述存储器单元的误差校正数据指示所述存储器单元中存储的阈值电压的特定阈值电压范围内的相对位置。

公开(公告)号：US11443797B2

公开(公告)日：2022-09-13

申请号：US16798166

申请日：2020-02-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Shu-Yin Ho ,  Hsiang-Pang Li ,  Yao-Wen Kang ,  Chun-Feng Wu ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C11/54 ,  G11C11/4091 ,  G06N3/06 ,  G06N3/08 ,  G06F7/544 ,  G11C11/408 ,  G11C11/4094

Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

公开(公告)号：US20200312405A1

公开(公告)日：2020-10-01

申请号：US16798166

申请日：2020-02-21

Applicant: MACRONIX International Co., Ltd.

Inventor： SHU-YIN HO ,  Hsiang-Pang Li ,  Yao-Wen Kang ,  Chun-Feng Wu ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C11/54 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G06N3/06 ,  G06N3/08 ,  G06F7/544

Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

公开(公告)号：US10447436B2

公开(公告)日：2019-10-15

申请号：US15890500

申请日：2018-02-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Huang ,  Chih-Huai Shih ,  Hsiang-Pang Li ,  Hsi-Chia Chang

IPC: H04L1/00 ,  H03M13/00 ,  H03M13/13

Abstract: A method for generating a polar code includes the steps of: establishing a plurality of polarization matrices that receive a plurality of first input bits via a plurality of first input channels and provide a plurality of first output bits on a plurality of first output channels; selecting at least one to-be-enhanced input channel from the first input channels of the polarization matrices; providing a re-polarization matrix that receives a plurality of second input bits via a plurality of second input channels and provides a plurality of second output bits on a plurality of second output channels, wherein a part of the second output bits is used as the first output bit(s) on the at least one to-be-enhanced input channel; and providing a polar code that comprises the first output bits and a remaining part of the second output bits.

公开(公告)号：US20190050156A1

公开(公告)日：2019-02-14

申请号：US15672430

申请日：2017-08-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06 ,  G06F12/02 ,  G11C7/04

Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.

公开(公告)号：US10128982B2

公开(公告)日：2018-11-13

申请号：US15287120

申请日：2016-10-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Huang ,  Hsiang-Pang Li ,  Hsie-Chia Chang

IPC: H03M13/00 ,  H04L1/00 ,  H03M13/13

Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N−K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q−K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q−K frozen bits are allocated to the N−K frozen bit-channels and the q additional frozen bit-channels.

公开(公告)号：US10120605B2

公开(公告)日：2018-11-06

申请号：US15093841

申请日：2016-04-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Yu-Ming Chang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56

Abstract: A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.

公开(公告)号：US09740602B2

公开(公告)日：2017-08-22

申请号：US14805498

申请日：2015-07-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F12/00 ,  G11C11/56 ,  G11C16/10 ,  G11C16/04

CPC classification number: G06F12/00 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7209 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.

公开(公告)号：US20170052899A1

公开(公告)日：2017-02-23

申请号：US14828587

申请日：2015-08-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ye-Jyun Lin ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Chia-Lin Yang

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0897 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0685 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/1044 ,  G06F2212/225

Abstract: A buffer cache device used to get at least one data from at least one application is provided, wherein the buffer cache device includes a first-level cache memory, a second-level cache memory and a controller. The first-level cache memory is used to receive and store the data. The second-level cache memory has a memory cell architecture different from that of the first-level cache memory. The controller is used to write the data stored in the first-level cache memory into the second-level cache memory.

Abstract translation: 提供了用于从至少一个应用获得至少一个数据的缓冲器高速缓存设备，其中缓冲器高速缓存设备包括第一级高速缓冲存储器，二级高速缓存存储器和控制器。 第一级高速缓存用于接收和存储数据。 第二级高速缓冲存储器具有与第一级高速缓冲存储器不同的存储单元架构。 控制器用于将存储在第一级高速缓冲存储器中的数据写入二级高速缓冲存储器。

公开(公告)号：US09501396B2

公开(公告)日：2016-11-22

申请号：US13969462

申请日：2013-08-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Cheng-Yuan Wang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Pi-Cheng Hsiu ,  Tei-Wei Kuo

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F12/109 ,  G06F2212/1032 ,  G06F2212/7204 ,  G06F2212/7211

Abstract: A method for managing utilization of a memory including a physical address space comprises mapping logical addresses of data objects to locations within the physical address space, and defining a plurality of address segments in the space as an active window. The method comprises allowing writes of data objects having logical addresses mapped to locations within the plurality of address segments in the active window. The method comprises, upon detection of a request to write a data object having a logical address mapped to a location outside the active window, updating the mapping so that the logical address maps to a selected location within the active window, and then allowing the write to the selected location. The method comprises maintaining access data indicating utilization of the plurality of address segments in the active window, and adding and removing address segments from the active window in response to the access data.

Abstract translation: 一种用于管理包括物理地址空间的存储器的利用的方法包括将数据对象的逻辑地址映射到物理地址空间内的位置，以及将空间中的多个地址段定义为活动窗口。 该方法包括允许将具有映射到活动窗口中的多个地址段内的位置的逻辑地址的数据对象的写入。 该方法包括在检测到写入具有映射到活动窗口之外的位置的逻辑地址的数据对象的请求时，更新映射，使得逻辑地址映射到活动窗口内的选定位置，然后允许写入 到所选位置。 该方法包括维护指示在活动窗口中多个地址段的利用的访问数据，以及响应于访问数据从活动窗口添加和移除地址段。