公开(公告)号：US08164115B2

公开(公告)日：2012-04-24

申请号：US13010238

申请日：2011-01-20

申请人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L21/337 ,  H01L21/335

CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/432 ,  H01L29/66462

摘要： A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.

摘要翻译： 氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅电极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。 所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。

公开(公告)号：US08076698B2

公开(公告)日：2011-12-13

申请号：US11995040

申请日：2006-06-27

申请人： Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Masahiro Hikita ,  Hiroaki Ueno

发明人： Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Masahiro Hikita ,  Hiroaki Ueno

IPC分类号： H01L31/0328

CPC分类号： H01L29/739 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7786

摘要： In a transistor, an AlN buffer layer 102, an undoped GaN layer 103, an undoped AlGaN layer 104, a p-type control layer 105, and a p-type contact layer 106 are formed in this order on a sapphire substrate 101. The transistor further includes a gate electrode 110 in ohmic contact with the p-type contact layer 106, and a source electrode 108 and a drain electrode 109 provided on the undoped AlGaN layer 104. By applying a positive voltage to the p-type control layer 105, holes are injected into a channel to increase a current flowing in the channel.

摘要翻译： 在晶体管中，在蓝宝石衬底101上依次形成AlN缓冲层102，未掺杂的GaN层103，未掺杂的AlGaN层104，p型控制层105和p型接触层106。 晶体管还包括与p型接触层106欧姆接触的栅电极110以及设置在未掺杂的AlGaN层104上的源电极108和漏极109.通过向p型控制层105施加正电压 ，孔被注入到通道中以增加在通道中流动的电流。

公开(公告)号：US07825434B2

公开(公告)日：2010-11-02

申请号：US11647218

申请日：2006-12-29

申请人： Hiroaki Ueno ,  Manabu Yanagihara ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Hiroaki Ueno ,  Manabu Yanagihara ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L29/08

CPC分类号： H01L29/7783 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/432 ,  H01L29/452 ,  H01L29/7787

摘要： A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.

摘要翻译： 氮化物半导体器件包括：由第一氮化物半导体制成的第一半导体层; 第二半导体层，其形成在第一半导体层的主表面上并且由具有比第一氮化物半导体的带隙宽的第二氮化物半导体构成; 选择性地形成在所述第二半导体层的上部并且由上述第二半导体层的上部制成的具有p型导电性的第三氮化物半导体的控制层; 源极和漏极，形成在控制层的相应侧上的第二半导体层上; 形成在所述控制层上的栅电极; 以及第四半导体层，形成在与所述主表面相对的所述第一半导体层的表面上，相对于所述第一氮化物半导体具有价带中的势垒，并且由包含铝的第四氮化物半导体构成。

公开(公告)号：US07759700B2

公开(公告)日：2010-07-20

申请号：US11593016

申请日：2006-11-06

申请人： Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L31/0256

CPC分类号： H01L29/7787 ,  H01L23/3732 ,  H01L29/2003 ,  H01L29/66462 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a first group-III nitride semiconductor layer formed on a substrate; a second group-III nitride semiconductor layer made of a single layer or two or more layers, formed on the first group-III nitride semiconductor layer, and acting as a barrier layer; a source electrode, a drain electrode, and a gate electrode formed on the second group-III nitride semiconductor layer, the gate electrode controlling a current flowing between the source and drain electrodes; and a heat radiation film with high thermal conductivity which covers, as a surface passivation film, the entire surface other than a bonding pad.

摘要翻译： 半导体器件包括：形成在衬底上的第一III族氮化物半导体层; 形成在第一III族氮化物半导体层上并且用作阻挡层的由单层或两层或更多层制成的第二III族氮化物半导体层; 形成在所述第二III族氮化物半导体层上的源电极，漏电极和栅极，所述栅电极控制在所述源极和漏极之间流动的电流; 以及具有高导热性的热辐射膜，其覆盖除了焊盘之外的整个表面作为表面钝化膜。

公开(公告)号：US07576373B1

公开(公告)日：2009-08-18

申请号：US11595966

申请日：2006-11-13

申请人： Masahiro Hikita ,  Manabu Yanagihara ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Manabu Yanagihara ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L31/72

CPC分类号： H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462

摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a first p-AlGaN layer, a second p-AlGaN layer and a high concentration p-GaN layer are formed in this order on a substrate. A gate electrode establishes ohmic contact with the high concentration p-GaN layer. A source electrode and a drain electrode are formed on the undoped AlGaN layer. Two-dimensional electron gas generated at the interface between the undoped AlGaN layer and the undoped GaN layer and the first and second p-AlGaN layers form a pn junction in a gate region. The second p-AlGaN layer covers a SiN film in part.

摘要翻译： 在衬底上依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，第一p-AlGaN层，第二p-AlGaN层和高浓度p-GaN层。 栅电极与高浓度p-GaN层建立欧姆接触。 在未掺杂的AlGaN层上形成源电极和漏电极。 在未掺杂的AlGaN层和未掺杂的GaN层之间的界面处产生的二维电子气和第一和第二p-AlGaN层在栅极区域中形成pn结。 第二p-AlGaN层部分覆盖SiN膜。

公开(公告)号：US20080079023A1

公开(公告)日：2008-04-03

申请号：US11890480

申请日：2007-08-07

申请人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L21/337 ,  H01L21/335

CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/432 ,  H01L29/66462

摘要： A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.

摘要翻译： 氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅电极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。 所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。

公开(公告)号：US07291872B2

公开(公告)日：2007-11-06

申请号：US11193417

申请日：2005-08-01

申请人： Masahiro Hikita ,  Hiroaki Ueno ,  Yutaka Hirose ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Hiroaki Ueno ,  Yutaka Hirose ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L31/00

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4175

摘要： In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.

摘要翻译： 在本发明的半导体器件的结构中，第一源极通过通孔与导电性基板连接，形成第二源电极。 因此，即使在栅电极和漏电极之间施加高的反向电压，也可以有效地分散或放松更靠近漏电极的栅电极的边缘处可能发生的电场集中。 此外，导电性基板用作形成元件形成层的基板，从而不必在导电性基板上形成贯穿基板到达其背面的通路孔。 因此，由于保持导电基板所需的强度，第一源电极可以电连接到背面电极。

公开(公告)号：US20070235768A1

公开(公告)日：2007-10-11

申请号：US11730422

申请日：2007-04-02

申请人： Kazushi Nakazawa ,  Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Kazushi Nakazawa ,  Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L27/10

CPC分类号： H01L29/872 ,  H01L29/2003 ,  H01L29/66212

摘要： A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.

摘要翻译： 半导体器件包括：由III族氮化物半导体制成并具有与第一表面相对的第一表面和第二表面的半导体层; 形成在半导体层的第一表面上的肖特基电极; 以及与半导体层的第二表面电连接的欧姆电极。 半导体层至少在其上部具有选择性地形成为具有高电阻的高电阻区域。

公开(公告)号：US08592866B2

公开(公告)日：2013-11-26

申请号：US11600102

申请日：2006-11-16

申请人： Manabu Yanagihara ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Manabu Yanagihara ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L29/66

CPC分类号： H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/432 ,  H01L29/66462

摘要： A transistor includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer, a control layer formed on the second semiconductor layer and contains p-type impurities, a gate electrode formed in contact with at least part of the control layer and a source electrode and a drain electrode formed on both sides of the control layer, respectively. A third semiconductor layer made of material having a lower etch rate than that of the control layer is formed between the control layer and the second semiconductor layer.

摘要翻译： 晶体管包括形成在基板上的第一半导体层，形成在第一半导体层上并具有比第一半导体层的带隙大的带隙的第二半导体层，形成在第二半导体层上并包含p型 杂质，形成为与控制层的至少一部分接触的栅极电极以及分别形成在控制层两侧的源电极和漏电极。 在控制层和第二半导体层之间形成由蚀刻率低于控制层的材料制成的第三半导体层。

公开(公告)号：US08264002B2

公开(公告)日：2012-09-11

申请号：US12880704

申请日：2010-09-13

申请人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L29/7786 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

摘要翻译： 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。