公开(公告)号：US20070235768A1

公开(公告)日：2007-10-11

申请号：US11730422

申请日：2007-04-02

申请人： Kazushi Nakazawa ,  Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Kazushi Nakazawa ,  Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L27/10

CPC分类号： H01L29/872 ,  H01L29/2003 ,  H01L29/66212

摘要： A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.

摘要翻译： 半导体器件包括：由III族氮化物半导体制成并具有与第一表面相对的第一表面和第二表面的半导体层; 形成在半导体层的第一表面上的肖特基电极; 以及与半导体层的第二表面电连接的欧姆电极。 半导体层至少在其上部具有选择性地形成为具有高电阻的高电阻区域。

公开(公告)号：US07605441B2

公开(公告)日：2009-10-20

申请号：US11730422

申请日：2007-04-02

申请人： Kazushi Nakazawa ,  Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Kazushi Nakazawa ,  Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L27/095 ,  H01L21/28 ,  H01L29/47

CPC分类号： H01L29/872 ,  H01L29/2003 ,  H01L29/66212

摘要： A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.

摘要翻译： 半导体器件包括：由III族氮化物半导体制成并具有与第一表面相对的第一表面和第二表面的半导体层; 形成在半导体层的第一表面上的肖特基电极; 以及与半导体层的第二表面电连接的欧姆电极。 半导体层至少在其上部具有选择性地形成为具有高电阻的高电阻区域。

公开(公告)号：US07528423B2

公开(公告)日：2009-05-05

申请号：US11681408

申请日：2007-03-02

申请人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

发明人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

IPC分类号： H01L31/072 ,  H01L31/109

CPC分类号： H01L29/7786 ,  H01L29/2003

摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.

摘要翻译： 本发明的一个目的是提供一种可以同时实现HFET的常闭模式和改进Imax的半导体器件，并进一步实现gm的改善和栅极漏电流的减小。 为了在栅电极正下方的基板11的操作层12上保持薄的阻挡层13，主要用于实现常关模式并且还实现了高的Imax，它被配置成使得厚度 可以通过栅极和源极区域之间以及栅极和漏极区域之间的半导体层17来增加阻挡层13。 因此，与设置阻挡层的厚度均匀的FET相比，可以实现常闭模式和Imax的改善。 介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而可以实现gm的改善和栅极漏电流的减小。

公开(公告)号：US20060157729A1

公开(公告)日：2006-07-20

申请号：US11325340

申请日：2006-01-05

申请人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

发明人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

IPC分类号： H01L33/00

CPC分类号： H01L29/7786 ,  H01L29/2003

摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.

摘要翻译： 本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善 和栅极漏电流的减小。 为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max， 配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。 因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。 介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅泄漏电流的降低 可以实现。

公开(公告)号：US20060060895A1

公开(公告)日：2006-03-23

申请号：US11193417

申请日：2005-08-01

申请人： Masahiro Hikita ,  Hiroaki Ueno ,  Yutaka Hirose ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Hiroaki Ueno ,  Yutaka Hirose ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L31/112 ,  H01L29/20 ,  H01L29/80

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4175

摘要： In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.

摘要翻译： 在本发明的半导体器件的结构中，第一源极通过通孔与导电性基板连接，形成第二源电极。 因此，即使在栅电极和漏极之间施加高的反向电压，也可以有效地分散或放松在栅电极的靠近漏电极的边缘处可能发生的电场集中。 此外，导电性基板用作形成元件形成层的基板，从而不必在导电性基板上形成贯穿基板到达其背面的通路孔。 因此，由于保持导电基板所需的强度，第一源电极可以电连接到背面电极。

公开(公告)号：US08203376B2

公开(公告)日：2012-06-19

申请号：US12445390

申请日：2007-11-20

申请人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H03K17/687

CPC分类号： H01L29/7787 ,  H01L27/0605 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/739 ,  H01L29/8124

摘要： A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.

摘要翻译： 半导体器件包括形成在衬底11上并具有沟道区的半导体层堆叠13，在半导体层叠层13上彼此隔开形成的第一电极16A和第二电极16B，形成在第一栅电极18A之间的第一栅电极18A 第一电极16A和第二电极16B，以及形成在第一栅电极18A和第二电极16B之间的第二栅电极18B。 在半导体层堆叠13和第一栅电极18A之间形成具有p型导电性的第一控制层19A。

公开(公告)号：US08076698B2

公开(公告)日：2011-12-13

申请号：US11995040

申请日：2006-06-27

申请人： Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Masahiro Hikita ,  Hiroaki Ueno

发明人： Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Masahiro Hikita ,  Hiroaki Ueno

IPC分类号： H01L31/0328

CPC分类号： H01L29/739 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7786

摘要： In a transistor, an AlN buffer layer 102, an undoped GaN layer 103, an undoped AlGaN layer 104, a p-type control layer 105, and a p-type contact layer 106 are formed in this order on a sapphire substrate 101. The transistor further includes a gate electrode 110 in ohmic contact with the p-type contact layer 106, and a source electrode 108 and a drain electrode 109 provided on the undoped AlGaN layer 104. By applying a positive voltage to the p-type control layer 105, holes are injected into a channel to increase a current flowing in the channel.

摘要翻译： 在晶体管中，在蓝宝石衬底101上依次形成AlN缓冲层102，未掺杂的GaN层103，未掺杂的AlGaN层104，p型控制层105和p型接触层106。 晶体管还包括与p型接触层106欧姆接触的栅电极110以及设置在未掺杂的AlGaN层104上的源电极108和漏极109.通过向p型控制层105施加正电压 ，孔被注入到通道中以增加在通道中流动的电流。

公开(公告)号：US07825434B2

公开(公告)日：2010-11-02

申请号：US11647218

申请日：2006-12-29

申请人： Hiroaki Ueno ,  Manabu Yanagihara ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Hiroaki Ueno ,  Manabu Yanagihara ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L29/08

CPC分类号： H01L29/7783 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/432 ,  H01L29/452 ,  H01L29/7787

摘要： A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.

摘要翻译： 氮化物半导体器件包括：由第一氮化物半导体制成的第一半导体层; 第二半导体层，其形成在第一半导体层的主表面上并且由具有比第一氮化物半导体的带隙宽的第二氮化物半导体构成; 选择性地形成在所述第二半导体层的上部并且由上述第二半导体层的上部制成的具有p型导电性的第三氮化物半导体的控制层; 源极和漏极，形成在控制层的相应侧上的第二半导体层上; 形成在所述控制层上的栅电极; 以及第四半导体层，形成在与所述主表面相对的所述第一半导体层的表面上，相对于所述第一氮化物半导体具有价带中的势垒，并且由包含铝的第四氮化物半导体构成。

公开(公告)号：US07759700B2

公开(公告)日：2010-07-20

申请号：US11593016

申请日：2006-11-06

申请人： Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Hiroaki Ueno ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L31/0256

CPC分类号： H01L29/7787 ,  H01L23/3732 ,  H01L29/2003 ,  H01L29/66462 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a first group-III nitride semiconductor layer formed on a substrate; a second group-III nitride semiconductor layer made of a single layer or two or more layers, formed on the first group-III nitride semiconductor layer, and acting as a barrier layer; a source electrode, a drain electrode, and a gate electrode formed on the second group-III nitride semiconductor layer, the gate electrode controlling a current flowing between the source and drain electrodes; and a heat radiation film with high thermal conductivity which covers, as a surface passivation film, the entire surface other than a bonding pad.

摘要翻译： 半导体器件包括：形成在衬底上的第一III族氮化物半导体层; 形成在第一III族氮化物半导体层上并且用作阻挡层的由单层或两层或更多层制成的第二III族氮化物半导体层; 形成在所述第二III族氮化物半导体层上的源电极，漏电极和栅极，所述栅电极控制在所述源极和漏极之间流动的电流; 以及具有高导热性的热辐射膜，其覆盖除了焊盘之外的整个表面作为表面钝化膜。

公开(公告)号：US07291872B2

公开(公告)日：2007-11-06

申请号：US11193417

申请日：2005-08-01

申请人： Masahiro Hikita ,  Hiroaki Ueno ,  Yutaka Hirose ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Hiroaki Ueno ,  Yutaka Hirose ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L31/00

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4175

摘要： In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.

摘要翻译： 在本发明的半导体器件的结构中，第一源极通过通孔与导电性基板连接，形成第二源电极。 因此，即使在栅电极和漏电极之间施加高的反向电压，也可以有效地分散或放松更靠近漏电极的栅电极的边缘处可能发生的电场集中。 此外，导电性基板用作形成元件形成层的基板，从而不必在导电性基板上形成贯穿基板到达其背面的通路孔。 因此，由于保持导电基板所需的强度，第一源电极可以电连接到背面电极。