公开(公告)号：US07375552B1

公开(公告)日：2008-05-20

申请号：US11151892

申请日：2005-06-14

申请人： Steven P. Young ,  Trevor J. Bauer ,  Manoj Chirania ,  Venu M. Kondapalli

发明人： Steven P. Young ,  Trevor J. Bauer ,  Manoj Chirania ,  Venu M. Kondapalli

IPC分类号： H03K19/177 ,  G06F7/38

CPC分类号： H03K19/17736 ,  G06F7/5324 ,  G06F7/5443 ,  H03K19/17728

摘要： A programmable logic block provides two lookup table (LUT) output signals to a general interconnect structure in an integrated circuit (IC), one output terminal of the logic block being dedicated to a first LUT output signal, and the other output terminal having a selectable input that can provide either of the two LUT output signals to the general interconnect structure. An IC includes an interconnect structure (e.g., a programmable interconnect structure) and a programmable logic block coupled to the interconnect structure. The programmable logic block includes a LUT having two output terminals. A first LUT output terminal is non-programmably coupled to the interconnect structure via a first output terminal of the logic block. Both the first and the second LUT output terminals are programmably coupled to the interconnect structure via a second output terminal of the logic block, e.g., via a programmable multiplexer selecting between the two LUT output terminals.

摘要翻译： 可编程逻辑块向集成电路（IC）中的通用互连结构提供两个查找表（LUT）输出信号，逻辑块的一个输出端专用于第一LUT输出信号，另一个输出端具有可选择的 可以将两个LUT输出信号中的任一个提供给通用互连结构的输入。 IC包括互连结构（例如，可编程互连结构）和耦合到互连结构的可编程逻辑块。 可编程逻辑块包括具有两个输出端的LUT。 第一LUT输出端子经由逻辑块的第一输出端子不可编程地耦合到互连结构。 第一和第二LUT输出端子都可以通过逻辑块的第二输出端子可编程地耦合到互连结构，例如经由可编程多路复用器在两个LUT输出端子之间进行选择。

公开(公告)号：US07353487B1

公开(公告)日：2008-04-01

申请号：US10981877

申请日：2004-11-05

申请人： Jason R. Bergendahl ,  Ping-Chen Liu ,  Paul T. Sasaki ,  Suresh M. Menon ,  Atul V. Ghia ,  Steven P. Young ,  Trevor J. Bauer

发明人： Jason R. Bergendahl ,  Ping-Chen Liu ,  Paul T. Sasaki ,  Suresh M. Menon ,  Atul V. Ghia ,  Steven P. Young ,  Trevor J. Bauer

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F2217/62

摘要： Signal distribution of a regional signal is described. A programmable logic device includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.

摘要翻译： 描述区域信号的信号分布。 可编程逻辑器件包括全局信号分配网络，区域信号分配网络和区域缓冲器。 区域缓冲区具有耦合在区域信号分配网络末端的输出。 区域信号分配网络通过互连瓦片耦合到可配置的逻辑块。 区域缓冲器耦合到具有区域时钟的输入/输出块。 另外描述了用于区域信号分配的源同步接口。

公开(公告)号：US07265576B1

公开(公告)日：2007-09-04

申请号：US11152736

申请日：2005-06-14

申请人： Venu M. Kondapalli ,  Trevor J. Bauer ,  Manoj Chirania ,  Philip D. Costello ,  Steven P. Young

发明人： Venu M. Kondapalli ,  Trevor J. Bauer ,  Manoj Chirania ,  Philip D. Costello ,  Steven P. Young

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  H03K19/17728

摘要： A programmable lookup table optionally provides two input signals and two output signals to an interconnect structure of a programmable integrated circuit when programmed to function as a random access memory (RAM). An integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure. The LUT can be configured to function as a single-bit wide RAM (e.g., a (2**N)×1 RAM) having N input address signals coupled to the interconnect structure and one output signal coupled to the interconnect structure, or as a multi-bit wide RAM (e.g., a (2**(N−1))×2 RAM) having fewer than N (e.g., N−1) input address signals coupled to the interconnect structure and at least two output signals coupled to the interconnect structure. Optionally, the LUT can also be configured as shift register logic, e.g., a 2**(N−1)-bit shift register or two 2**(N−2)-bit shift registers.

摘要翻译： 当编程为用作随机存取存储器（RAM）时，可编程查找表可选地向可编程集成电路的互连结构提供两个输入信号和两个输出信号。 集成电路包括互连结构和具有耦合到互连结构的输入和输出端子的N输入查找表（LUT）。 LUT可以被配置为用作具有耦合到互连结构的N个输入地址信号和耦合到互连结构的一个输出信号的单位宽RAM（例如，（2 ** N）x1 RAM），或者作为 具有小于N（例如，N-1）个输入地址信号的耦合到互连结构的多位宽RAM（例如，（2 **（N-1））×2 RAM）以及耦合到互连结构的至少两个输出信号 互连结构。 可选地，LUT也可以被配置为移位寄存器逻辑，例如2 **（N-1）位移位寄存器或两个2 **（N-2）位移位寄存器。

公开(公告)号：US07057413B1

公开(公告)日：2006-06-06

申请号：US10853419

申请日：2004-05-24

申请人： Steven P. Young ,  Peter H. Alfke ,  Trevor J. Bauer ,  Colm P. Fewer

发明人： Steven P. Young ,  Peter H. Alfke ,  Trevor J. Bauer ,  Colm P. Fewer

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H04Q3/0004 ,  H04Q3/521 ,  H04Q2213/13076

摘要： A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch, the input signals only carry crossbar switch data, and the connectivity is controlled by FPGA configuration data. The crossbar switch is implemented in two parts: a template of basic and constant routing to carry input signals through the switch array in one dimension and output signals from the array in another dimension, and a connectivity part controlled by a connectivity table or algorithm to generate partial reconfiguration bitstreams that determine which of the input signals is to be connected to which of the output signals.

摘要翻译： 描述了使用FPGA实现交叉开关的方法。 不是使用通过通用FPGA路由资源路由的信号来控制交叉开关的连接，而是输入信号只带有交叉开关数据，连接由FPGA配置数据控制。 交叉开关分两部分实现：基本和恒定路由的模板，通过一维的开关阵列传送输入信号，并在另一维度上输出阵列的信号，以及由连接表或算法控制的连接部分，以产生 部分重新配置比特流，其确定哪个输入信号要连接到哪个输出信号。

公开(公告)号：US06621296B2

公开(公告)日：2003-09-16

申请号：US10295713

申请日：2002-11-15

申请人： Richard A. Carberry ,  Steven P. Young ,  Trevor J. Bauer

发明人： Richard A. Carberry ,  Steven P. Young ,  Trevor J. Bauer

IPC分类号： G06F738

CPC分类号： H03K19/17728 ,  H03K19/1737

摘要： A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The read decoder includes a multiplexing circuit made up of a series of multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and a second LUT.

摘要翻译： 用于可编程逻辑器件（PLD）的快速，节省空间的查找表（LUT），其中修改LUT的写解码器，读取解码器和存储器块以提供高性能，同时提供高效布局。 写解码器和读取解码器都由LUT输入信号控制，数据信号被直接发送到存储器块的每个存储电路（即不经过写入解码器）。 读取解码器包括由一系列多路复用器组成的复用电路，该多路复用器由从PLD的互连资源接收的输入信号直接控制。 在一个实施例中，可配置逻辑块被提供有由第一LUT和第二LUT共享的单个写入解码器。

公开(公告)号：US06362648B1

公开(公告)日：2002-03-26

申请号：US09712038

申请日：2000-11-13

申请人： Bernard J. New ,  Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

发明人： Bernard J. New ,  Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

IPC分类号： G06F738

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1778

摘要： The invention allows the implementation of common wide logic functions using only two function generators of a field programmable gate array. One embodiment of the invention provides a structure for implementing a wide AND-gate in an FPGA configurable logic element (CLE) or portion thereof that includes no more than two function generators. First and second function generators are configured as AND-gates, the output signals (first and second AND signals) being combined in a 2-to-1 multiplexer controlled by the first AND signal, “0” selecting the first AND signal and “1” selecting the second AND signal. Therefore, a wide AND-gate is provided having a number of input signals equal to the total number of input signals for the two function generators. In another embodiment, a wide OR-gate is provided by configuring the function generators as OR-gates and controlling the multiplexer using the second OR signal.

摘要翻译： 本发明允许仅使用现场可编程门阵列的两个函数发生器实现普通的宽逻辑功能。 本发明的一个实施例提供了一种用于在FPGA可配置逻辑元件（CLE）或其部分中实现宽的与门的结构，其包括不超过两个功能发生器。 第一和第二功能发生器被配置为与门，输出信号（第一和第二AND信号）被组合在由第一AND信号控制的2对1多路复用器中，选择第一AND信号为“0”和“1” “选择第二个AND信号。 因此，提供了具有等于两个功能发生器的输入信号的总数的多个输入信号的宽AND门。 在另一个实施例中，通过将功能发生器配置为OR门并使用第二OR信号来控制多路复用器来提供宽的或门。

公开(公告)号：US06323682B1

公开(公告)日：2001-11-27

申请号：US09574534

申请日：2000-05-19

申请人： Trevor J. Bauer ,  Steven P. Young

发明人： Trevor J. Bauer ,  Steven P. Young

IPC分类号： H03K19177

CPC分类号： H03K19/1736 ,  G11C19/00 ,  H03K19/17736 ,  H03K19/1776

摘要： A hierarchy of multiplexers is provided to generate functions of more inputs than the lookup table can handle. For example, a lookup table having 16 memory cells can generate functions of four input signals. By combining the outputs of two lookup tables in a multiplexer (F5) controlled by a fifth input signal, any function of five input signals can be generated. Using a sixth signal to select between the outputs of two such F5 multiplexers allows any function of six input signals to be generated, and so forth. In one embodiment, a configurable logic block (CLB) includes four slices, each having two four-input lookup tables (a total of eight lookup tables). The multiplexer hierarchy allows for all functions of eight input signals to be generated by selecting the output signal of one of the 16 lookup tables in a pair of CLBs. In addition to the eight lookup tables that generate functions of four input signals, the CLB includes four F5 multiplexers, where each F5 multiplexer receives input signals from two lookup tables and can generate all functions of five input signals when the two lookup tables receive the same four input signals and the F5 multiplexer is controlled by the fifth input signal. The CLB also includes two F6 multiplexers where each F6 multiplexer receives input signals from two of the F5 multiplexers. The CLB further includes an F7 multiplexer which receives the two F6 signals. The CLB also includes an F8 multiplexer which receives the F7 multiplexer output signal and an F7 multiplexer output signal from an adjacent CLB.

摘要翻译： 提供多路复用器的层次结构以生成比查找表可处理的更多的输入的函数。 例如，具有16个存储单元的查找表可以生成四个输入信号的功能。 通过组合由第五输入信号控制的多路复用器（F5）中的两个查找表的输出，可以生成五个输入信号的任何功能。 使用第六信号在两个这样的F5多路复用器的输出之间进行选择允许产生六个输入信号的任何功能，等等。 在一个实施例中，可配置逻辑块（CLB）包括四个片，每片具有两个四输入查找表（总共八个查找表）。 复用器层次结构允许通过选择一对CLB中的16个查找表中的一个的输出信号来生成八个输入信号的所有功能。 除了产生四个输入信号功能的八个查找表之外，CLB还包括四个F5多路复用器，其中每个F5多路复用器从两个查找表接收输入信号，并且当两个查找表接收到相同时，可以生成五个输入信号的所有功能 四路输入信号和F5多路复用器由第五输入信号控制。 CLB还包括两个F6复用器，其中每个F6多路复用器接收来自两个F5多路复用器的输入信号。 CLB还包括接收两个F6信号的F7复用器。 CLB还包括F8多路复用器，其接收F7多路复用器输出信号和来自相邻CLB的F7多路复用器输出信号。

公开(公告)号：US06292022B1

公开(公告)日：2001-09-18

申请号：US09759051

申请日：2001-01-11

申请人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

发明人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

IPC分类号： H01L2500

摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.

公开(公告)号：US6124731A

公开(公告)日：2000-09-26

申请号：US480845

申请日：2000-01-10

申请人： Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

发明人： Steven P. Young ,  Shekhar Bapat ,  Kamal Chaudhary ,  Trevor J. Bauer ,  Roman Iwanczuk

IPC分类号： H01L25/00 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17728 ,  H03K19/1737 ,  H03K19/17704

摘要： The invention provides a Configurable Logic Element (CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four function generators. The outputs of two function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs, or some functions of up to nine inputs. The outputs of the other two function generators are similarly combined. The outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a six-input-function multiplexer or function generator. The six-input-function multiplexer or function generator therefore produces an output that can be any function of up to six inputs. Some functions of up to nineteen inputs can also be generated in a single CLE.

摘要翻译： 本发明提供了优选地包括在相同瓦片的阵列中的每一个中的可配置逻辑元件（CLE）。 根据本发明的CLE具有四个功能发生器。 两个功能发生器的输出与五输入功能多路复用器或函数发生器中的第五个独立输入相结合，以产生可以是五个输入或多达九个输入的一些功能的输出。 其他两个功能发生器的输出类似地组合。 然后，两个五输入功能多路复用器或函数发生器的输出与六输入函数多路复用器或函数发生器中的第六个独立输入相组合。 因此，六输入功能多路复用器或函数发生器产生的输出可以是多达六个输入的任何功能。 也可以在单个CLE中生成多达十九个输入的某些功能。

公开(公告)号：US6072348A

公开(公告)日：2000-06-06

申请号：US890952

申请日：1997-07-09

申请人： Bernard J. New ,  Trevor J. Bauer ,  Steven P. Young

发明人： Bernard J. New ,  Trevor J. Bauer ,  Steven P. Young

IPC分类号： G06F1/08 ,  G06F1/32 ,  H03K1/04

CPC分类号： G06F1/32 ,  G06F1/08

摘要： A clock distribution circuit and method for programmable ICs whereby the incoming clock frequency is optionally divided by two and distributed at the new, lower frequency. Programmable dual-edge/single-edge flip-flops are provided that optionally operate at twice the frequency of the distributed clock, being responsive to both rising and falling edges of the distributed clock. When the clock divider is enabled and the flip-flops are programmed as dual-edge, the operating frequency is the same as that of the incoming clock; however, the frequency of the distributed clock is reduced by one-half. This reduction halves the frequency at which the clock distribution circuits operate, and consequently approximately halves the power dissipated by the clock distribution circuit, thereby providing a programmable power-saving mode.

摘要翻译： 一种用于可编程IC的时钟分配电路和方法，其中输入时钟频率可选地被二分频并以新的较低频率分布。 提供了可编程双边沿/单边沿触发器，可选地以分布式时钟频率的两倍工作，响应于分布式时钟的上升沿和下降沿。 当时钟分频器使能并且触发器被编程为双边沿时，工作频率与输入时钟的工作频率相同; 然而，分布式时钟的频率减少了一半。 这种减少将时钟分配电路工作的频率减半，从而将时钟分配电路消耗的功率大致减半，从而提供可编程省电模式。