公开(公告)号：US4187473A

公开(公告)日：1980-02-05

申请号：US903422

申请日：1978-05-08

Applicant: Michael J. Cochran

Inventor： Michael J. Cochran

IPC: H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03H17/00 ,  H03L7/091 ,  H03L7/18 ,  H03L7/183 ,  H04B1/40 ,  H04W84/00 ,  H03B3/04

CPC classification number: H04W84/00 ,  H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03L7/091 ,  H03L7/183 ,  H04B1/40

Abstract: An electronic phase locked loop circuit including a variable period sawtooth generator. The sawtooth generator receives digital reference clock signals and in response thereto generates sawtooth-shaped signals having the same period as said reference clock signals. A sample and hold circuit samples the sawtooth-shaped signals in response to one logical state of a sampling clock. A voltage controlled oscillator is coupled to the output of the sample and hold circuit and oscillates at a frequency proportional to the magnitude of the held sample. A feedback circuit generates the sampling clock by coupling the output of the voltage controlled oscillator to the sampling input of the sample and hold circuit.

Abstract translation: 一种包括可变周期锯齿波发生器的电子锁相环电路。 锯齿波发生器接收数字参考时钟信号，响应于此产生具有与所述参考时钟信号相同周期的锯齿形信号。 采样和保持电路响应于采样时钟的一个逻辑状态对锯齿形信号进行采样。 压控振荡器耦合到采样和保持电路的输出，并以与被保持的样本的幅度成正比的频率振荡。 反馈电路通过将压控振荡器的输出耦合到采样和保持电路的采样输入端产生采样时钟。

公开(公告)号：US4164037A

公开(公告)日：1979-08-07

申请号：US736271

申请日：1976-10-27

Applicant: Michael J. Cochran ,  Charles P. Grant, Jr., deceased

Inventor： Michael J. Cochran ,  Charles P. Grant, Jr., deceased

IPC: G06F15/02

CPC classification number: G06F15/02

Abstract: An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is provided with a semiconductor chip having a memory for storing instruction words, an arithmetic unit, an instruction word decoder for controlling the arithmetic unit in response to instruction commands read out of the instruction word memory and a combined data and flag bit storage system. The combined data and flag bit storage system provides for the storage of flag bits with an associated numeric data word in a single register. Certain of the stages of the register are preferably dedicated for use as flag bit storage and certain other stages of the register are dedicated for use as numeric data storage. The arithmetic unit is preferably operable in a first mode for performing arithmetic operations in binary coded decimal format for the numeric data and in a binary format for the flag bits.

Abstract translation: 具有优选地具有键盘输入和视觉显示的类型的电子计算器或微处理器系统设置有具有用于存储指令字的存储器的半导体芯片，运算单元，用于响应于读取指令命令来控制算术单元的指令字解码器 指令字存储器和组合数据和标志位存储系统。 组合的数据和标志位存储系统提供在单个寄存器中存储与相关联的数字数据字的标志位。 寄存器的某些阶段优选专用于用作标志位存储，并且寄存器的某些其它级专用于数字数据存储。 算术单元优选地可以以用于数字数据的二进制编码十进制格式和用于标志位的二进制格式执行算术运算的第一模式。

公开(公告)号：US4145756A

公开(公告)日：1979-03-20

申请号：US748076

申请日：1976-12-06

Applicant: Michael J. Cochran ,  Stephen P. Hamilton

Inventor： Michael J. Cochran ,  Stephen P. Hamilton

IPC: G06K15/02 ,  G08B5/36

CPC classification number: G06K15/028

Abstract: A thermal printer system for actuating a plurality of groups of thermal printing elements. The system includes a first circuit in which a plurality of data words are stored, the words representing the characters to be printed. A second circuit converts the data words into printing character codes. A selected bit from each code, which bit is sequentially altered, is supplied to a third circuit for actuating the printing elements.

Abstract translation: 一种用于致动多组热敏打印元件的热敏打印机系统。 该系统包括其中存储多个数据字的第一电路，表示要打印的字符的字。 第二个电路将数据字转换成打印字符代码。 来自每个代码的选择的位被顺序地改变，被提供给用于致动打印元件的第三电路。

公开(公告)号：US4145656A

公开(公告)日：1979-03-20

申请号：US791253

申请日：1977-04-27

Applicant: Jerry D. Merryman ,  Michael J. Cochran ,  Edward R. Caudel

Inventor： Jerry D. Merryman ,  Michael J. Cochran ,  Edward R. Caudel

IPC: H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03H17/00 ,  H03L7/091 ,  H03L7/18 ,  H03L7/183 ,  H04B1/40 ,  H04W84/00 ,  H04B1/38

CPC classification number: H04W84/00 ,  H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03L7/091 ,  H03L7/183 ,  H04B1/40

Abstract: A transceiver receives electronic input signals comprised of a plurality of frequency bands lying within a plurality of non-overlapping frequency channels. A mixer frequency shifts a selected band to a predetermined center frequency in response to a first clocking signal of a first selectable frequency. A charge transfer device filter is coupled to the mixer output to filter the band of the predetermined center frequency in response to a second selectable frequency clocking signal. The clocking signals are generated by clocking means which receive digital microcommands identifying the selectable frequencies. Signal level measuring means are coupled to the output of the charge transfer device filter and generate digital level signals indicating the signal level present in the filtered band. Microprocessor means are coupled to send microcommands to the clocking means for sequentially filtering various channels from the plurality, and for monitoring the resulting digital level signals.

Abstract translation: 收发机接收由位于多个非重叠频率信道内的多个频带组成的电子输入信号。 混频器响应于第一可选择频率的第一时钟信号将所选频带移位到预定的中心频率。 电荷转移装置滤波器耦合到混频器输出端，以响应于第二可选频率时钟信号对预定中心频率的频带进行滤波。 时钟信号由接收识别可选择频率的数字微型命令的计时装置产生。 信号电平测量装置耦合到电荷转移装置滤波器的输出，并产生指示滤波频带中存在的信号电平的数字电平信号。 微处理器装置被耦合以将微指令发送到时钟装置，用于顺序地从多个通道中滤除各种通道，并用于监视所得到的数字电平信号。

公开(公告)号：US4132951A

公开(公告)日：1979-01-02

申请号：US791254

申请日：1977-04-27

Applicant: Michael J. Cochran ,  Edward R. Caudel

Inventor： Michael J. Cochran ,  Edward R. Caudel

IPC: H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03H17/00 ,  H03L7/091 ,  H03L7/18 ,  H03L7/183 ,  H04B1/40 ,  H04W84/00 ,  H04B1/06

CPC classification number: H04W84/00 ,  H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03L7/091 ,  H03L7/183 ,  H04B1/40

Abstract: A radio system includes a charge transfer device transversal filter for receiving electronic input signals comprised of at least one frequency band. The charge transfer device simultaneously receives a clocking signal, and filters and frequency shifts its input signals in response to the frequency of the clocking signal. Clocking means are provided for generating the clocking signal at frequencies as indicated in digital micro commands. A digital processor has outputs coupled to the clocking means for sending the micro commands to the clocking means.

公开(公告)号：US4126831A

公开(公告)日：1978-11-21

申请号：US791264

申请日：1977-04-27

Applicant: Michael J. Cochran

Inventor： Michael J. Cochran

IPC: H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03H17/00 ,  H03L7/091 ,  H03L7/18 ,  H03L7/183 ,  H04B1/40 ,  H04W84/00 ,  H03B3/04

CPC classification number: H04W84/00 ,  H03D1/24 ,  H03D7/00 ,  H03H15/02 ,  H03L7/091 ,  H03L7/183 ,  H04B1/40

Abstract: An electronic phase detector circuit includes a variable period sawtooth generator. The sawtooth generator receives digital reference clock signals and in response thereto generates sawtooth-shaped signals having the same period as said reference clock signals. A sample and hold circuit samples the sawtooth-shaped signals in response to one logical state of a sampling clock. A voltage controlled oscillator is coupled to the output of the sample and hold circuit and oscillates at a frequency proportional to the magnitude of the held sample.

Abstract translation: 电子相位检测器电路包括可变周期锯齿波发生器。 锯齿波发生器接收数字参考时钟信号，响应于此产生具有与所述参考时钟信号相同周期的锯齿形信号。 采样和保持电路响应于采样时钟的一个逻辑状态对锯齿形信号进行采样。 压控振荡器耦合到采样和保持电路的输出，并以与被保持的样本的幅度成正比的频率振荡。

公开(公告)号：US4125830A

公开(公告)日：1978-11-14

申请号：US658793

申请日：1976-02-17

Applicant: Michael J. Cochran ,  Stephen P. Hamilton

Inventor： Michael J. Cochran ,  Stephen P. Hamilton

IPC: G09G3/14 ,  G06K15/18

CPC classification number: G09G3/14

Abstract: An alphanumeric display system which may be implemented on one or more semiconductor chips for controlling display devices arrayed in N groups, each group of which comprises an A by B matrix of devices and which is capable of displaying a single alphanumeric character. The display devices in each group are sequentially addressed with display commands being communicated therewith in a predetermined manner to cause the display devices to visually display a predetermined alphanumeric character. Use of the alphanumeric display system herein disclosed, permits a total of A by B by N display devices to be controlled by the display system using as few as A + B + N connecting conductors to control the display devices and associated display driver devices.

Abstract translation: 可以在一个或多个半导体芯片上实现的用于控制以N组排列的显示设备的字母数字显示系统，每个组包括设备的A乘B矩阵，并且能够显示单个字母数字字符。 每组中的显示装置按照预定方式与显示命令进行顺序寻址，以使显示装置可视地显示预定的字母数字字符。 使用本文公开的字母数字显示系统，允许N显示设备的总共A乘B由显示系统使用少至A + B + N连接导体来控制显示设备和相关显示驱动器设备。

公开(公告)号：US4048624A

公开(公告)日：1977-09-13

申请号：US593611

申请日：1975-07-07

Applicant: Michael J. Cochran ,  Charles P. Grant, Jr.

Inventor： Michael J. Cochran ,  Charles P. Grant, Jr.

IPC: G06F15/02 ,  G06F15/78 ,  G06F1/00 ,  G06F9/00

CPC classification number: G06F15/7835 ,  G06F15/02

Abstract: A calculator system, implemented on at least one semiconductor chip and having a read-only-memory for storing a plurality of program instructions, has a multi-function memory instruction register. The instruction register has a parallel input for receiving a selected program instruction from the memory, and preferably a parallel output for transmitting the program instruction to a decoder. The instruction register also has a serial output connected to a buffer. The memory is addressed by an address register which also provides a code indicative of whether or not the addressed program instruction is to control the calculator system. When the addressed program instruction is to control the system, the code has preselected setting and the program instruction is read out of the instruction register through the buffer and is sequentially serially re-entered into the instruction register via a serial input. Thereafter, the program instruction is read out of the instruction register to be decoded by the decoder. In a multi-chip system, each of the plurality of chips has a read-only-memory for storing a plurality of program instructions, an aforementioned multi-function memory instruction register and associated buffer, and the serial inputs of the instruction registers of the plurality of chips are connected in common. One chip is selected by the preselected setting of the code and program instructions of the selected chip are read out to all of the instruction registers implemented on the plurality of chips via the common connection.

公开(公告)号：US3984816A

公开(公告)日：1976-10-05

申请号：US607525

申请日：1975-08-25

Applicant: Michael J. Cochran ,  Jerry L. Vandierendonck

Inventor： Michael J. Cochran ,  Jerry L. Vandierendonck

IPC: G06F3/02

CPC classification number: G06F3/0227

Abstract: An electronic portable calculator implemented in MOS/LSI technology and including a scanned keyboard input and display output. The calculator system utilizes a plurality of output terinals on the primary MOS/LSI chip for selectively addressing in timed coded sequence an array of peripheral MOS/LSI chips providing for expanded register and memory capacity and for output printing. Data registers are provided in a sequentially addressed random access memory array, which is addressed by a commutator also used to generate encoded timing signals for other parts of the system and control logic. The keyboard input includes an interface register into which is entered key sense line information along with encoded timing information derived from the encoded timing signals. The contents of the interface register may be entered into the data registers or used to select an address in a program storage memory via a program counter. Bits may be read out in parallel from cells in the data registers and processed through an arithmetic logic unit and then re-entered in the same cells within a bit time or state time, so the data registers do not recirculate in the usual sense.

Abstract translation: 一种以MOS / LSI技术实现的电子便携式计算机，包括扫描的键盘输入和显示输出。 计算器系统利用主MOS / LSI芯片上的多个输出端，以定时编码顺序有选择地寻址提供扩展寄存器和存储器容量并用于输出打印的外围MOS / LSI芯片阵列。 数据寄存器被提供在顺序寻址的随机存取存储器阵列中，其由换向器寻址，该换向器也用于为系统的其他部分和控制逻辑生成编码定时信号。 键盘输入包括接口寄存器，其中输入了键传感线信息以及从经编码的定时信号导出的编码定时信息。 接口寄存器的内容可以输入到数据寄存器中，或者用于通过程序计数器选择程序存储存储器中的地址。 位可以从数据寄存器中的单元并行读出并通过算术逻辑单元进行读出，然后在位时间或状态时间内重新输入到相同的单元中，因此数据寄存器在通常的意义上不再循环。

公开(公告)号：US07095181B2

公开(公告)日：2006-08-22

申请号：US10087154

申请日：2002-03-01

Applicant: John R. Frus ,  Michael J. Cochran

Inventor： John R. Frus ,  Michael J. Cochran

IPC: H05B37/02

CPC classification number: F02P15/10 ,  F02P3/08 ,  F02P3/0869 ,  F02P3/0892 ,  F02P9/002 ,  F02P9/007 ,  F02P15/003 ,  F02P15/08 ,  F02P17/12

Abstract: An apparatus for controllably generating sparks is provided. The apparatus includes a spark generating device; at least two output stages connected to the spark generating device; means for charging energy storage devices in the output stages and at least partially isolating each of the energy storage devices from the energy storage devices of the other output stages; and, a logic circuit for selectively triggering the output stages to generate a spark. Each of the output stages preferably includes: (1) an energy storage device to store the energy; (2) a controlled switch for selectively discharging the energy storage device; and (3) a network for transferring the energy discharged by the energy storage device to the spark generating device. In accordance with one aspect of the invention, the logic circuit, which is connected to the controlled switches of the output stages, can be configured to fire the stages at different times, in different orders, and/or in different combinations to provide the spark generating device with output pulses having substantially any desired waveshape and energy level to thereby produce a spark having substantially any desired energy level and plume shape at the spark generating device to suit any application.