公开(公告)号：US6057713A

公开(公告)日：2000-05-02

申请号：US38751

申请日：1998-03-12

申请人： Michael R. May ,  John E. Willis

发明人： Michael R. May ,  John E. Willis

IPC分类号： G11C27/02

CPC分类号： G11C27/024

摘要： Method and apparatus for performing voltage sampling. The present invention addresses the problems encountered when a voltage is applied to a voltage sampling circuit (76). An additional capacitor (88) is used to store an amount of charge similar to the amount of charge needed by a primary capacitor (89) which provides an output signal to a voltage receiving circuit (74), such as a portion of a sigma-delta analog to digital converter. The additional capacitor (88) is charged while a primary capacitor (89) is discharged in a first clock phase. Then the additional capacitor (88) and the primary capacitor (89) are both coupled to the voltage to be sampled during a second clock phase.

摘要翻译： 用于执行电压采样的方法和装置。 本发明解决了当将电压施加到电压采样电路（76）时遇到的问题。 附加电容器（88）用于存储类似于向电压接收电路（74）提供输出信号的主电容器（89）所需的电荷量，所述电荷量例如是Σ- delta模数转换器。 当在第一时钟相位中放电初级电容器（89）时，附加电容器（88）被充电。 然后，在第二时钟相位期间，附加电容器（88）和初级电容器（89）都耦合到要采样的电压。

公开(公告)号：US5727038A

公开(公告)日：1998-03-10

申请号：US707828

申请日：1996-09-06

申请人： Michael R. May ,  Michael D. Cave

发明人： Michael R. May ,  Michael D. Cave

IPC分类号： H03D13/00 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/191 ,  H03D3/24

CPC分类号： H03D13/004 ,  H03L7/089 ,  H03L7/0997 ,  H03L7/191 ,  H03L2207/50 ,  H03L7/093

摘要： A phase locked loop (10) with a phase detector (11), a digital loop filter (12), a digital controlled oscillator (13) and a divide-by-N circuit (14) generates a periodic signal which has a predetermined phase and voltage related to a reference clock signal. A phase and frequency detector (21) outputs an average of error between a feedback delay clock and a reference clock to the digital loop filter (12). The digital loop filter (12) processes the phase detector (11) output and the inband quantization noise utilizing a sigma delta converter. The digital loop filter (12) utilizes a non binary weight scheme to minimize the number of bits changing states. The digital controlled oscillator (13) generates a loop clock signal utilizing a plurality of digital programmable delay elements. A divide-by-N circuit (14) performs a divide by 2560.

摘要翻译： 具有相位检测器（11），数字环路滤波器（12），数字控制振荡器（13）和N分频电路（14）的锁相环（10）产生具有预定相位的周期信号 和与参考时钟信号有关的电压。 相位和频率检测器（21）将反馈延迟时钟和参考时钟之间的误差的平均值输出到数字环路滤波器（12）。 数字环路滤波器（12）利用Σ-Δ转换器处理相位检测器（11）输出和带内量化噪声。 数字环路滤波器（12）利用非二进制加权方案来最小化位数改变状态。 数字控制振荡器（13）利用多个数字可编程延迟元件产生环路时钟信号。 N分频电路（14）执行除法2560。

公开(公告)号：US5530383A

公开(公告)日：1996-06-25

申请号：US349586

申请日：1994-12-05

申请人： Michael R. May

发明人： Michael R. May

IPC分类号： H03L7/095 ,  H03L7/097 ,  H03D3/24

CPC分类号： H03L7/095 ,  Y10S331/02

摘要： A frequency lock indicator (10) comprises a first delay (14), second delay (20), first sampler (24), second sampler (28), third sampler (32), fourth sampler (34), and lock indicator (36). The first delay (14) delays a rising edge of a frequency reference (12) which clocks the first sampler (24) on a rising edge and the third sampler (32) on a falling edge. The second delay (20) delays a rising edge of a feedback signal (18) to produce a delayed feedback signal (22) which clocks the second sampler (28) on a rising edge and the fourth sampler (34) on a falling edge. The first and third samplers sample an up-pump signal (26) and the second and fourth samplers sample a down-pump signal (30). The lock indicator (36) produces a lock indication signal (38) when the sampled up-pump signal substantially equal to the sampled down-pump signal.

摘要翻译： 频率锁定指示器（10）包括第一延迟（14），第二延迟（20），第一采样器（24），第二采样器（28），第三采样器（32），第四采样器（34）和锁定指示器 ）。 第一延迟（14）延迟在上升沿对时钟第一采样器（24）的频率参考（12）的上升沿和在下降沿上延迟第三采样器（32）。 第二延迟（20）延迟反馈信号（18）的上升沿以产生延迟反馈信号（22），其在上升沿对第二取样器（28）进行计时，并且第四采样器（34）在下降沿上进行计时。 第一和第三采样器对上泵信号（26）进行采样，第二和第四采样器对下泵信号（30）进行采样。 当采样的上升泵信号基本上等于采样的下降泵信号时，锁定指示器（36）产生锁定指示信号（38）。

公开(公告)号：US08811929B2

公开(公告)日：2014-08-19

申请号：US11265867

申请日：2005-11-03

申请人： Jon David Hendrix ,  Michael R. May

发明人： Jon David Hendrix ,  Michael R. May

IPC分类号： H04B1/16

CPC分类号： H04B1/1607 ,  H03G3/20 ,  H04B1/1018 ,  H04W52/0245 ,  Y02D70/00

摘要： A method for managing power of a battery-powered handheld audio device by receiving an indicia of signal quality for a received continuous-time radio signal. The method compares the indicia of signal quality to a signal quality threshold. Upon a favorable comparison, enacting a first analog signal conditioning setting. Upon an unfavorable comparison, enacting a second analog signal conditioning setting. The method further provides, upon the favorable comparison, disabling a digital filtering operation, and upon the unfavorable comparison, enabling the digital filtering operation.

摘要翻译： 一种用于通过接收所接收的连续时间无线电信号的信号质量标记来管理电池供电的手持音频设备的电力的方法。 该方法将信号质量的标记与信号质量阈值进行比较。 在有利的比较下，颁布第一个模拟信号调节设置。 在不利的比较下，执行第二模拟信号调节设置。 该方法进一步提供了有利的比较，禁用数字滤波操作，并且在不利的比较中，实现数字滤波操作。

公开(公告)号：US08774328B2

公开(公告)日：2014-07-08

申请号：US12894316

申请日：2010-09-30

申请人： Javier Elenes ,  Brian D. Green ,  Michael R. May

发明人： Javier Elenes ,  Brian D. Green ,  Michael R. May

IPC分类号： H03D1/00

CPC分类号： H04B1/086 ,  H04H20/30 ,  H04H60/12 ,  H04H2201/18 ,  H04L25/03834 ,  H04L27/0008 ,  H04W52/0229 ,  Y02D70/00

摘要： In one embodiment, a receiver front end circuit can receive and process multiple radio frequency (RF) signals and output downconverted signals corresponding to these signals. In turn, multiple signal processors can be coupled to this front end. Specifically, a first signal processor can receive and process the downconverted signals to output a first signal obtained from content of a first RF signal, and a second signal processor can receive and process the downconverted signals to output a second signal obtained from content of a second RF signal. In addition, the apparatus may include a detection circuit coupled to the receiver front end circuit to detect presence of at least the second signal and enable the second signal processor responsive to the detected presence.

摘要翻译： 在一个实施例中，接收器前端电路可以接收和处理多个射频（RF）信号并输出​​与这些信号对应的下变频信号。 反过来，多个信号处理器可以耦合到该前端。 具体地，第一信号处理器可以接收并处理下变频信号以输出从第一RF信号的内容获得的第一信号，并且第二信号处理器可以接收并处理下变频信号以输出从第二RF信号的内容获得的第二信号 射频信号。 此外，该装置可以包括耦合到接收器前端电路的检测电路，以检测至少第二信号的存在，并使第二信号处理器能够响应于检测到的存在。

公开(公告)号：US08538365B2

公开(公告)日：2013-09-17

申请号：US13249508

申请日：2011-09-30

申请人： Russell Croman ,  Christopher S. Gregg ,  Dan B. Kasha ,  Michael R. May ,  John Khoury ,  Javier Elenes

发明人： Russell Croman ,  Christopher S. Gregg ,  Dan B. Kasha ,  Michael R. May ,  John Khoury ,  Javier Elenes

IPC分类号： H04B1/10

CPC分类号： H04W52/0238 ,  H04B1/06 ,  H04W52/0245 ,  Y02D70/40

摘要： In one embodiment, a method includes receiving and processing an incoming radio frequency (RF) signal in a receiver. Based on this signal, an environmental noise level can be determined, where this level corresponds to environmental noise present in an environment in which the receiver is located. Then, if the environmental noise level is substantially greater than receiver-generated noise, power consumption of at least one analog front end component of the receiver can be reduced.

摘要翻译： 在一个实施例中，一种方法包括在接收机中接收和处理输入射频（RF）信号。 基于该信号，可以确定环境噪声电平，其中该电平对应于存在于接收器所处的环境中的环境噪声。 然后，如果环境噪声电平显着大于接收器产生的噪声，则可以减少接收机的至少一个模拟前端部件的功耗。

公开(公告)号：US20120082271A1

公开(公告)日：2012-04-05

申请号：US12894316

申请日：2010-09-30

申请人： JAVIER ELENES ,  Brian D. Green ,  Michael R. May

发明人： JAVIER ELENES ,  Brian D. Green ,  Michael R. May

IPC分类号： H04L27/06

CPC分类号： H04B1/086 ,  H04H20/30 ,  H04H60/12 ,  H04H2201/18 ,  H04L25/03834 ,  H04L27/0008 ,  H04W52/0229 ,  Y02D70/00

摘要： In one embodiment, a receiver front end circuit can receive and process multiple radio frequency (RF) signals and output downconverted signals corresponding to these signals. In turn, multiple signal processors can be coupled to this front end. Specifically, a first signal processor can receive and process the downconverted signals to output a first signal obtained from content of a first RF signal, and a second signal processor can receive and process the downconverted signals to output a second signal obtained from content of a second RF signal. In addition, the apparatus may include a detection circuit coupled to the receiver front end circuit to detect presence of at least the second signal and enable the second signal processor responsive to the detected presence.

摘要翻译： 在一个实施例中，接收器前端电路可以接收和处理多个射频（RF）信号并输出​​与这些信号对应的下变频信号。 反过来，多个信号处理器可以耦合到该前端。 具体地，第一信号处理器可以接收并处理下变频信号以输出从第一RF信号的内容获得的第一信号，并且第二信号处理器可以接收并处理下变频信号以输出从第二RF信号的内容获得的第二信号 射频信号。 此外，该装置可以包括耦合到接收器前端电路的检测电路，以检测至少第二信号的存在，并使第二信号处理器能够响应于检测到的存在。

公开(公告)号：US07620380B2

公开(公告)日：2009-11-17

申请号：US11388795

申请日：2006-03-24

申请人： Jon David Hendrix ,  Michael R. May

发明人： Jon David Hendrix ,  Michael R. May

IPC分类号： H04B1/06

CPC分类号： H04B1/28

摘要： A method for adjusting automatic gain control (AGC) of a radio receiver begins when a primary AGC module establishes an AGC setting for the radio receiver to produce a primary AGC setting. The method continues when a supervisory AGC module compares performance of the radio receiver utilizing the primary AGC setting with a plurality of performance thresholds. The method continues with the supervisory AGC module adjusting the primary AGC setting to produce adjusted AGC setting when the performance of the radio receiver utilizing the primary AGC setting compares unfavorable with a first performance threshold of the plurality of performance thresholds. The method continues with the supervisory AGC module overwriting the primary AGC setting with alternative AGC setting when the performance of the radio receiver utilizing the primary AGC setting compares unfavorable with a second performance threshold of the plurality of performance thresholds.

摘要翻译： 一种用于调整无线电接收机的自动增益控制（AGC）的方法，当主AGC模块建立无线电接收机的AGC设置以产生主AGC设置时，开始。 当监控AGC模块使用主AGC设置与多个性能阈值比较无线电接收机的性能时，继续该方法。 当使用主AGC设置的无线电接收机的性能与多个性能阈值的第一性能阈值不利时相比较时，继续监视AGC模块调整主AGC设置以产生调整的AGC设置。 当使用主AGC设置的无线电接收机的性能与多个性能阈值的第二性能阈值相比较时，该方法继续，监控AGC模块用替代的AGC设置覆盖主AGC设置。

公开(公告)号：US07599451B2

公开(公告)日：2009-10-06

申请号：US11126832

申请日：2005-05-11

申请人： Michael R. May

发明人： Michael R. May

IPC分类号： H04L27/06 ,  H03M7/00

CPC分类号： H04L25/05 ,  H03H17/0286 ,  H03H17/0614 ,  H03H17/0621 ,  H04L27/142 ,  H04L2027/0024 ,  H04L2027/0087

摘要： A sample rate converter includes an upsampling module, a low pass filter, and a linear sample rate conversion module. The upsampling module is operably coupled up-sample a digital input signal having a first rate to produce a digitally up-sampled signal. The low pass filter is operably coupled to low pass filter the digitally up-sampled signal to produce a digitally filtered signal at an up-sampled rate. The linear sample rate conversion module is operably coupled to convert the digitally up-sampled signal into a sample rate adjusted digital signal having a second rate based on an control feedback signal and a linear function, wherein a relationship between the first rate and the second rate is a non-power of two.

摘要翻译： 采样率转换器包括上采样模块，低通滤波器和线性采样率转换模块。 上采样模块可操作地耦合上采样具有第一速率的数字输入信号以产生数字上采样信号。 低通滤波器可操作地耦合到低通滤波器的数字上采样信号，以产生以上采样速率的数字滤波信号。 线性采样率转换模块可操作地耦合以将数字上采样信号转换为基于控制反馈信号和线性函数的具有第二速率的采样率调整数字信号，其中第一速率与第二速率之间的关系 是一个没有力量的两个。

公开(公告)号：US07515078B2

公开(公告)日：2009-04-07

申请号：US11728812

申请日：2007-03-26

申请人： Michael R. May

发明人： Michael R. May

IPC分类号： H03M3/00

CPC分类号： H03H17/0671 ,  H03M3/454 ,  H03M3/498

摘要： A programmable sample rate ADC includes a delta sigma modulator for producing a digital signal, and a programmable decimation filter, that includes X stages of integration, a down-sampling stage for down-sampling by a factor of N, and Y stages of differentiation. The programmable sample rate ADC produces a digital output signal at a substantially constant frequency.

摘要翻译： 可编程采样率ADC包括用于产生数字信号的Δ-Σ调制器和可编程抽取滤波器，其包括X级积分，用于以N因子进行下采样的下采样级和Y级差分。 可编程采样率ADC以基本恒定的频率产生数字输出信号。