Abstract:
A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.
Abstract:
A method of failure recovery in a network element is disclosed. The method includes indicating to a number of forwarding engines that a forwarding engine has completed a switchover operation and causing at least one of the forwarding engines to acknowledge that the forwarding engine has completed the switchover operation in response to the indication.
Abstract:
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being lined with a trapping material. The trench is filled with an oxide dielectric material and a control gate is formed over the oxide-filled trench. Source/drain regions are adjacent the trench sides with the trapping material. An energy barrier between the drain and source regions has two local high points that correspond to the trench corners. To read the device, sufficient gate voltage is applied to invert the channel and a sufficient drain voltage is applied to pull down the drain-side barrier. If charges of opposite polarity are trapped in the source-side trench corner, the source barrier will be significantly lowered so that current flows between source and drain under read conditions.
Abstract:
An apparatus for generating a fluid meniscus to be formed on a surface of a substrate is provided including a housing where the housing includes a housing surface to be placed proximate to a substrate surface of the substrate. The housing further includes a process configuration receiving region that is surrounded by the housing surface. The apparatus also includes a process configuration insert which has an insert surface where the process configuration insert is defined to fit within the process configuration receiving region of the housing such that the insert surface and the housing surface define a proximity face that can be placed proximate to the substrate surface of the substrate.
Abstract:
An efficient distributed architecture for forwarding packets. The packet to be forwarded arrives in an ingress port, is processed by an ingress forwarding engine, transferred to an egress forwarding engine, and then transmitted via an egress port. An address-based lookup at the ingress forwarding engine identifies the correct egress forwarding engine and also identifies a translation index specifying the forwarding equivalence class (e.g., combination of address prefix and mask) of the packet. The egress forwarding engine then uses the translation index as a memory pointer to recover adjacency information with which to rewrite the packet header. The egress forwarding engine may maintain its adjacency information entirely locally without the need to share the information or propagate updates to ingress forwarding engines. This approach results in a scalable and highly efficient packet forwarding architecture.