公开(公告)号：US11545199B2

公开(公告)日：2023-01-03

申请号：US17200233

申请日：2021-03-12

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/40 ,  G11C8/10

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

公开(公告)号：US11462254B2

公开(公告)日：2022-10-04

申请号：US17094731

申请日：2020-11-10

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Miles S. Wiscombe ,  James S. Rehmeyer ,  Eric J. Stave

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4074 ,  G11C5/14

Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

公开(公告)号：US20210263685A1

公开(公告)日：2021-08-26

申请号：US17315532

申请日：2021-05-10

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G06F3/06 ,  G11C7/10 ,  G11C11/4093

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.

公开(公告)号：US20210216479A1

公开(公告)日：2021-07-15

申请号：US16744091

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave

IPC: G06F13/16 ,  G06F13/40 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076

Abstract: Methods, systems, and devices for addressing scheme for a memory system are described. A memory system may include a plurality of memory devices that are coupled with various command address (CA) channels via respective pins. In some examples, different pins of each memory device may be coupled with different CA channels. When the memory system receives a command to enter a memory device into a per-device addressability (PDA) mode, certain CA channels may be driven. One or more memory devices may enter the PDA mode based on certain pins of the respective memory device being biased.

公开(公告)号：US10950282B2

公开(公告)日：2021-03-16

申请号：US16540011

申请日：2019-08-13

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/40 ,  G11C8/10

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

公开(公告)号：US10424356B2

公开(公告)日：2019-09-24

申请号：US16047954

申请日：2018-07-27

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/40 ,  G11C8/10

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

公开(公告)号：US11881245B2

公开(公告)日：2024-01-23

申请号：US17939908

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Miles S. Wiscombe ,  James S. Rehmeyer ,  Eric J. Stave

IPC: G11C11/4074 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4076 ,  G11C5/04

CPC classification number: G11C11/406 ,  G11C5/04 ,  G11C11/4074 ,  G11C11/4076

Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

公开(公告)号：US11867726B2

公开(公告)日：2024-01-09

申请号：US16985156

申请日：2020-08-04

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Stewart ,  Eric J. Stave ,  Matthew A. Prather

IPC: G01R13/32

CPC classification number: G01R13/32

Abstract: A method of operating an oscilloscope is disclosed. The method comprises providing a bit stream comprising pseudo-random data to an oscilloscope across a data path characterized by sufficient signal degradation to prevent the oscilloscope from reliably triggering a sweep of an eye pattern based on receiving the pseudo-random data; inserting a predetermined sequence of bits into the bit stream at predetermined periodic intervals to open the eye pattern sufficiently during each of the periodic intervals to permit the oscilloscope to trigger the sweep of the eye pattern; and generating the eye pattern based at least in part on the pseudo-random data and excluding the predetermined sequence of bits from the sweep of the eye pattern. Oscilloscopes configured to trigger according to a predetermined system of bits at predetermined intervals are also disclosed.

公开(公告)号：US20230386596A1

公开(公告)日：2023-11-30

申请号：US18109830

申请日：2023-02-14

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Luis Nathan Perez Acosta ,  Bryce A. Gardiner

IPC: G11C29/14 ,  G11C29/12

CPC classification number: G11C29/14 ,  G11C29/1201

Abstract: Interposers for use in testing and characterizing memory devices, such as memory devices including decision feedback equalization circuitry, are disclosed herein. In one embodiment, an apparatus includes an interposer having a first interface couplable to a memory device, a second interface couplable to one or more testers, and a channel circuit between the first interface and the second interface. The channel circuit is configurable, via one or more resistive elements, to change a measurable value of a signal transmitted between the first interface and the second interface via the channel circuit.

公开(公告)号：US11728001B2

公开(公告)日：2023-08-15

申请号：US17099694

申请日：2020-11-16

Applicant: Micron Technology, Inc.

Inventor： Markus H. Geiger ,  Anthony D. Newton ,  Ron A. Hughes ,  Eric J. Stave

IPC: G01R31/28 ,  G11C29/02 ,  G01R31/317 ,  G01R31/30 ,  G11C29/04

CPC classification number: G11C29/025 ,  G01R31/2818 ,  G01R31/2863 ,  G01R31/30 ,  G01R31/317 ,  G11C2029/0407

Abstract: Apparatuses for characterizing system channels and associated methods and systems are disclosed. In one embodiment, a tester is coupled to an adaptor configured to plug into a CPU socket of a system platform (e.g., a motherboard). The motherboard includes a memory socket that is connected to the CPU socket through system channels. The adaptor may include a connector configured to physically and electrically engage with the CPU socket, an interface configured to receive test signals from the tester, and circuitry configured to internally route the test signals to the connector. The adaptor, if plugged into the CPU socket, can facilitate the tester to directly assess signal transfer characteristics of the system channels. Accordingly, the tester can determine optimum operating parameters for the memory device in view of the system channel characteristics.