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公开(公告)号：US20250165310A1
公开(公告)日：2025-05-22
申请号：US18913696
申请日：2024-10-11
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
IPC: G06F9/50
Abstract: Resource can be managed by accessing, at a resource manager of a system, a leakage-temperature table. The resource manager can determine a dynamic resource pool and a static resource pool of the system based on the leakage-temperature table. The resource manager can receive a resource request from a device of the system. The resource manager can assign resources to the device from the dynamic resource pool and the static resource pool.
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公开(公告)号：US20250156271A1
公开(公告)日：2025-05-15
申请号：US18913708
申请日：2024-10-11
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Eyal En Gad
IPC: G06F11/10
Abstract: A syndrome can be calculated by storing data in a first array of memory cells and calculating syndromes utilizing the data, a first circuitry, and the first array of memory cells. The syndromes can be copied to a second array of memory cells. A decoding operation can be performed utilizing the plurality of syndromes, the second array of memory cells, and a second circuitry, where the first circuitry and the second circuitry are independent from each other.
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公开(公告)号：US20250155494A1
公开(公告)日：2025-05-15
申请号：US18918976
申请日：2024-10-17
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Evgeni Bassin
IPC: G01R31/28
Abstract: A method includes monitoring, by a temperature sensor, a temperature of a system on chip (SoC), determining temperature data of the SoC that includes an amount of time the SoC is operating at a plurality of different temperatures, normalizing the temperature data to a designated operating temperature, calculating an electromigration aging profile for the SoC based on the normalized temperature data, and determining a time-to-failure for the SoC based on the electromigration aging profile.
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公开(公告)号：US20250069679A1
公开(公告)日：2025-02-27
申请号：US18774638
申请日：2024-07-16
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
Abstract: A method includes determining a target total bit-error-rate (BER), calculating a target channel BER based on the target total BER, and training a channel to the calculated target channel BER by transmitting data over the channel in a loop from a physical input/output (PHY I/O) to a memory device, transmitting the test data over the channel in the loop from the memory device to the PHY I/O, wherein the data is looped from the memory device and back to the PHY I/O without being written to or road from the memory device, determining an actual channel BER based on the data transmitted to and received from the memory device, comparing the actual channel BER to the calculated target channel BER, and regulating a voltage value based on the comparison.
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公开(公告)号：US20240429904A1
公开(公告)日：2024-12-26
申请号：US18826526
申请日：2024-09-06
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.
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Patent Agency Ranking
公开(公告)号：US20240427511A1
公开(公告)日：2024-12-26
申请号：US18828263
申请日：2024-09-09
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Brian Toronyi
IPC: G06F3/06
Abstract: A first memory resource is configured to store a data structure. The first memory resource is coupled to a second memory resource that is configured to store a plurality of data structures. A processing device is coupled to the first memory resource, the second memory resource, and a third memory resource. The processing device writes data entries to the data structure within the first memory resource, determine that the data structure within the first memory resource includes a threshold quantity of data entries, and write the contents of the data structure within the first memory resource to a data structure within the second memory resource. The processing resource is further configured to move the contents of the contents of the data structure in the second memory resource to the third memory resource by readdressing the entries written within the second memory resource to virtual addresses associated with the third memory resource.
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公开(公告)号：US12169431B2
公开(公告)日：2024-12-17
申请号：US17893850
申请日：2022-08-23
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik
IPC: G06F1/3296 , G06F1/324
Abstract: An example method for voltage frequency scaling based on error rate can include performing a plurality of monitoring operations on a system on chip (SoC) at a respective plurality of voltage values (and/or plurality of frequency values and/or temperature values). The example method can include causing error rate data gathered from each of the plurality of monitoring operations to be entered into a database, wherein the entered error rate data is associated with the plurality of voltage values. The entered data is associated with the respective plurality of voltage value. The example method can include generating a plot using the error rate date in the database. The example method can include determining a particular voltage value greater than each of the plurality of voltage values based on the plot and a particular error rate associated with the particular voltage value.
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公开(公告)号：US12086440B2
公开(公告)日：2024-09-10
申请号：US17867396
申请日：2022-07-18
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Brian Toronyi
IPC: G06F3/06
CPC classification number: G06F3/0638 , G06F3/061 , G06F3/0683
Abstract: A first memory resource is configured to store a data structure. The first memory resource is coupled to a second memory resource that is configured to store a plurality of data structures. A processing device is coupled to the first memory resource, the second memory resource, and a third memory resource. The processing device writes data entries to the data structure within the first memory resource, determine that the data structure within the first memory resource includes a threshold quantity of data entries, and write the contents of the data structure within the first memory resource to a data structure within the second memory resource. The processing resource is further configured to move the contents of the contents of the data structure in the second memory resource to the third memory resource by readdressing the entries written within the second memory resource to virtual addresses associated with the third memory resource.
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公开(公告)号：US20240296118A1
公开(公告)日：2024-09-05
申请号：US18591851
申请日：2024-02-29
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik
CPC classification number: G06F12/0246 , G06F12/0653
Abstract: An apparatus includes a memory resource configured to store data entries in data structures including a first data structure and a second data structure and a processing device coupled to the memory resources. The processing device is configured to determine a predicted address location in the first data structure for a data entry, determine an equivalent address location in the second data structure, and write the data entry to the equivalent address location in the second data structure.
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公开(公告)号：US11888318B2
公开(公告)日：2024-01-30
申请号：US17715552
申请日：2022-04-07
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Ekram H. Bhuiyan
Abstract: Sensing circuitry and clock management circuitry provide transient load management. The sensing circuitry detects a voltage, current, and/or activity associated with a system-on-chip (SoC) and determines whether the detected voltage, current, and/or activity meets a threshold. The clock management circuitry generates clocking signals for the SoC and alters a frequency of the generated clocking signals in response to the detected voltage, current, and/or activity meeting the threshold to alter an amount of power consumed by the SoC.
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