公开(公告)号：US20240321380A1

公开(公告)日：2024-09-26

申请号：US18602782

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz

IPC: G11C29/50 ,  H03K3/037

CPC classification number: G11C29/50004 ,  H03K3/037 ,  G11C2029/5004

Abstract: A method includes supplying, via a voltage regulator, a supply voltage to a first voltage domain and a second voltage domain, detecting a change in an error characteristic of data associated with the second voltage domain, and altering the supply voltage to an altered supply voltage based on the change in the error characteristic.

公开(公告)号：US20240036596A1

公开(公告)日：2024-02-01

申请号：US17874867

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz ,  Ekram H. Bhuiyan

IPC: G05F1/575 ,  G11C5/14

CPC classification number: G05F1/575 ,  G11C5/147

Abstract: A first voltage regulation circuit is coupled to a second voltage regulation circuit. Control circuitry is coupled to the first voltage regulation circuit and the second voltage regulation circuit. The control circuitry determines that a signal criterion is met, and controls application of a voltage signal generated by the second voltage regulation circuit to stabilize a voltage signal generated by the first voltage regulation circuit.

公开(公告)号：US20240028244A1

公开(公告)日：2024-01-25

申请号：US17873046

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Yoav Weinberg ,  Nicola Pantaleo ,  Leonid Minz

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0679 ,  G06F3/0611

Abstract: Methods of operating memory systems with input/output expanders for multi-channel status reads (and associated systems and devices) are disclosed herein. In one embodiment, a method comprises receiving, via a controller-side communication channel, a multi-channel status read command at a first interface of an input/output expander. The method further comprises, based at least in part on receiving the multi-channel status read command, (a) transmitting, via a second interface of the input/output expander, a status read command to logical units over each of two or more memory-side channels; (b) receiving, at the second interface, status read data from the logical units over each memory-side channel of the two or more memory-side channels; and (c) transmitting, via the first interface, the status read data onto the controller-side communication channel.

公开(公告)号：US11815926B1

公开(公告)日：2023-11-14

申请号：US17887333

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz ,  Ekram H. Bhuiyan

IPC: G05F1/46 ,  G05F1/575 ,  G05F1/565

CPC classification number: G05F1/575 ,  G05F1/565

Abstract: A method includes receiving a respective signal from each of a plurality of respective sensor circuits, wherein each respective signal is indicative of a voltage or a current detected by each of the plurality of respective sensor circuits and performing an operation to determine whether one or more of the received signals meets a criterion. The method further includes generating a voltage management control signal in response to a determination that the one or more of the received signals meets the criterion, transferring the voltage management control signal to a voltage regulator, and generating, by the voltage regulator, a voltage signal in response to receipt of the voltage management control signal.

公开(公告)号：US20230327444A1

公开(公告)日：2023-10-12

申请号：US17715552

申请日：2022-04-07

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz ,  Ekram H. Bhuiyan

IPC: H02J3/14 ,  H02J3/02 ,  H02J3/24 ,  G06F1/324

CPC classification number: H02J3/14 ,  H02J3/02 ,  H02J3/241 ,  G06F1/324

Abstract: Sensing circuitry and clock management circuitry provide transient load management. The sensing circuitry detects a voltage, current, and/or activity associated with a system-on-chip (SoC) and determines whether the detected voltage, current, and/or activity meets a threshold. The clock management circuitry generates clocking signals for the SoC and alters a frequency of the generated clocking signals in response to the detected voltage, current, and/or activity meeting the threshold to alter an amount of power consumed by the SoC.

公开(公告)号：US20230290426A1

公开(公告)日：2023-09-14

申请号：US17692262

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz ,  Yoav Weinberg

IPC: G11C29/50

CPC classification number: G11C29/50004

Abstract: An example method for scan-based voltage frequency scaling can include performing a plurality of at-speed scan operation on a system on chip (SoC) at a plurality of respective voltage values. The example method can include entering data gathered from at least one of the plurality of at-speed scan operations into a database. The entered data is associated with the respective plurality of voltage value. The example method can include determining a particular voltage value of the respective plurality of voltage values at which a parameter of the SoC reaches a threshold. The example method can include indicating the determined particular voltage in the database. The indicated determined particular voltage in the database can be used for performing one or more operations using the SoC.

公开(公告)号：US20230289307A1

公开(公告)日：2023-09-14

申请号：US18119578

申请日：2023-03-09

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

IPC: G06F13/30 ,  G06F13/16

CPC classification number: G06F13/30 ,  G06F13/1668

Abstract: Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition, in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin, determining whether the logical level of the first pin changed from the first logical level to a second logical level, and in response to determining that the logical level of the first pin changed from the first logical to the second logical level, causing warmup cycles to be performed.

公开(公告)号：US11705173B1

公开(公告)日：2023-07-18

申请号：US17686940

申请日：2022-03-04

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz

IPC: G11C8/06 ,  H03M7/16 ,  H03M13/15 ,  H03M13/13

CPC classification number: G11C8/06 ,  H03M7/16 ,  H03M13/138 ,  H03M13/1575

Abstract: Memory units are accessed using address bits. The address bits used to access memory units can have various formats. The address bits to access successive locations that are to be sequentially accessed can have a reduced Hamming distance binary code format to reduce a quantity of toggling to switch from one set of address bits to another set of address bits.