公开(公告)号：US11293962B2

公开(公告)日：2022-04-05

申请号：US17015338

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley

IPC: G06F1/3225 ,  G01R27/26 ,  G06F1/3296 ,  G06F1/3234

Abstract: A memory sub-system includes a plurality of memory components where at least two of the memory components are configured to operate at different supply voltages. A capacitive voltage divider (CVD) configured to, responsive to a status of use of each of the memory components, select between a plurality of connections of a plurality of capacitors to reduce an input voltage of the memory sub-system. The plurality of connections is configured to provide different voltage magnitudes that correspond to the different supply voltages, and the CVD is further configured to output the different supply voltages to enable the use of each of the memory components.

公开(公告)号：US20210278893A1

公开(公告)日：2021-09-09

申请号：US17327282

申请日：2021-05-21

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley

IPC: G06F1/3296 ,  G06F13/20 ,  G06F13/40 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3221

Abstract: A power management integrated circuit (PMIC) is described for providing system management bus (SMB) isolation, along with memory sub-systems which include such a PMIC and methods of operating such devices. In one embodiment, a PMIC comprises a voltage supply input, power management circuitry, and elements of a SMB. The SMB elements can include an SMB input, an SMB hot swap controller coupled to the SMB input, one or more SMBs, and one or more SMB outputs. When integrated with a memory sub-system, one SMB output can be connected to a memory controller and another SMB output to a microcontroller. During different power states (e.g., normal or low power states), certain outputs can be isolated in order to manage communications on the SMB during the different power states of the memory sub-system using the PMIC.

公开(公告)号：US10922247B2

公开(公告)日：2021-02-16

申请号：US16540594

申请日：2019-08-14

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley ,  Peter R. Castro

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G11C7/10 ,  G06F12/02 ,  G06F3/06

Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

公开(公告)号：US20210034128A1

公开(公告)日：2021-02-04

申请号：US16524933

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： Vehid Suljic ,  Matthew D. Rowley

IPC: G06F1/28 ,  G11C5/14 ,  H02J7/34 ,  G06F3/06 ,  G06F1/30

Abstract: Various embodiments described herein use a plurality of capacitor sets (e.g., capacitor banks) in a power backup architecture for an electronic system (e.g., memory sub-system), where each capacitor set can be individually checked against a health condition (e.g., in parallel) to determine their respective health during power-up of an electronic system or during normal operation of the electronic system. In response to determining that at least one capacitor set has failed the health condition (or a certain number of capacitor sets have failed the health condition), the electronic system can perform certain operations prior to primary power loss to the electronic system (e.g., memory sub-system preemptively performs a data backup process to data integrity) and can adjust the operational mode of the electronic system (e.g., memory sub-system switches from read-write mode to read-only mode).

公开(公告)号：US20210034086A1

公开(公告)日：2021-02-04

申请号：US16525393

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley

IPC: G05F1/575 ,  H02M3/158

Abstract: Various embodiments described herein provide a system that uses a capacitor-based power converter to generate a gate voltage (e.g., boot strap voltage) for a buck converter. According to various embodiments described herein, the capacitor-based power converter includes at least one of a combination of a capacitive voltage divider circuit with a low-dropout (LDO) regulator, or a combination of a capacitive doubler circuit with an LDO regulator, to generate the gate voltage for the buck converter.

公开(公告)号：US20200072884A1

公开(公告)日：2020-03-05

申请号：US16119640

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley

IPC: G01R27/26 ,  G06F1/32

Abstract: A memory sub-system includes a plurality of memory components where at least two of the memory components are configured to operate at different supply voltages. A capacitive voltage divider (CVD) configured to, responsive to a status of use of each of the memory components, select between a plurality of connections of a plurality of capacitors to reduce an input voltage of the memory sub-system. The plurality of connections is configured to provide different voltage magnitudes that correspond to the different supply voltages, and the CVD is further configured to output the different supply voltages to enable the use of each of the memory components.

公开(公告)号：US20190373076A1

公开(公告)日：2019-12-05

申请号：US16540568

申请日：2019-08-14

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley ,  Mark Bauer

IPC: H04L29/08 ,  H04W88/06 ,  H04L29/06 ,  H04W88/16

Abstract: A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.

公开(公告)号：US10453541B1

公开(公告)日：2019-10-22

申请号：US16119488

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley ,  Michael J. Henderson

IPC: G11C16/30 ,  G11C5/14 ,  G05F1/46 ,  G06F1/28 ,  G01R19/165 ,  H02M3/07 ,  G11C16/10

Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage divider (CVD) coupled to the PMIC. The CVD is configured to receive the primary supply voltage of the memory sub-system as an input and provide a modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the MPSV is not higher than the uppermost PMIC supply voltage.

公开(公告)号：US10402351B2

公开(公告)日：2019-09-03

申请号：US16110171

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley ,  Peter R. Castro

IPC: G03F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F3/06

Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

公开(公告)号：US20190012280A1

公开(公告)日：2019-01-10

申请号：US16110171

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley ,  Peter R. Castro

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F3/06

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0626 ,  G06F3/0635 ,  G06F3/0649 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0683 ,  G06F12/0253 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1018 ,  G11C2207/107

Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.