公开(公告)号：US11481334B2

公开(公告)日：2022-10-25

申请号：US17319002

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/00 ,  G06F12/10 ,  H04L67/1097 ,  H04W84/04

Abstract: Systems, methods and apparatuses of distributed computing based on Memory as a Service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.

公开(公告)号：US11474828B2

公开(公告)日：2022-10-18

申请号：US16592547

申请日：2019-10-03

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F9/445 ,  G06F9/4401 ,  G06N3/08 ,  G06N3/04 ,  G06F12/06

Abstract: In a mobile device, processes of an application can be monitored and scored for initial data distribution. Specifically, a method can include monitoring processes of an application, and scoring objects or components used by the processes to determine placement of the objects or components in memory during initiation of the application. The method can also include, during initiation of the application, loading, into a first portion of the memory, at least partially, the objects or components scored at a first level. The method can also include, during initiation of the application, loading, into a second portion of the memory, at least partially, the objects or components scored at a second level. The objects or components scored at the second level can be less critical to the application than the objects or components scored at the first level.

公开(公告)号：US11416422B2

公开(公告)日：2022-08-16

申请号：US16573780

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivam Swami ,  Sean S. Eilert ,  Justin M. Eno ,  Ameen D. Akel

IPC: G06K7/08 ,  G06K19/06 ,  G06F13/10 ,  G06F3/06 ,  G06F13/12 ,  G06F12/0802

Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.

公开(公告)号：US20220237039A1

公开(公告)日：2022-07-28

申请号：US17723846

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Sean Stephen Eilert ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Dmitri Yudanov

IPC: G06F9/50 ,  H04L41/0896 ,  G06F12/02 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/08 ,  G06F12/1072 ,  G06F12/1036

Abstract: Systems, methods and apparatuses to throttle network communications for memory as a service are described. For example, a computing device can borrow an amount of random access memory of the lender device over a communication connection between the lender device and the computing device. The computing device can allocate virtual memory to applications running in the computing device, and configure at least a portion of the virtual memory to be hosted on the amount of memory loaned by the lender device to the computing device. The computing device can throttle data communications used by memory regions in accessing the amount of memory over the communication connection according to the criticality levels of the contents stored in the memory regions.

公开(公告)号：US11269780B2

公开(公告)日：2022-03-08

申请号：US16573541

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Sean S. Eilert ,  Hongyu Wang ,  Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Justin M. Eno ,  Shivam Swami

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/1027

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).

公开(公告)号：US11199977B2

公开(公告)日：2021-12-14

申请号：US16212540

申请日：2018-12-06

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/02

Abstract: A memory device having a memory array with a plurality of memory addresses and a controller operably coupled to the memory array is described. The controller is configured to store a sketch comprising d rows and w columns, wherein d and w are positive integers. Each of the d rows corresponds to a different one of d hash functions. The controller is also configured to detect an event associated with a first memory address of the plurality of memory addresses and to hash the first memory address with each of the d hash functions to generate a corresponding d sketch locations. The controller is further configured to adjust, for each of the d sketch locations, a stored sketch value by a first amount corresponding to the event.

公开(公告)号：US20210335445A1

公开(公告)日：2021-10-28

申请号：US17368651

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Justin Eno

IPC: G11C29/00 ,  G11C13/00 ,  G06F11/16 ,  G11C29/52

Abstract: Exemplary methods, apparatuses, and systems include determining that data in a group of memory cells of a first memory device is to be moved to a spare group of memory cells. The group of memory cells spans a first dimension and a second dimension that is orthogonal to the first dimension and the spare group of memory cells also spans the first dimension and the second dimension. The data is read from the group of memory cells along the first dimension of the group of memory cells. The data is written to the spare group of memory cells along the second dimension of the spare group of memory cells.

公开(公告)号：US11133061B2

公开(公告)日：2021-09-28

申请号：US16812559

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Edward C. McGlaughlin ,  Samuel E. Bradshaw

IPC: G06F13/00 ,  G11C13/00 ,  G06F3/06

Abstract: An example method includes determining a time between writes in place to a particular memory cell, incrementing a disturb count corresponding to a neighboring memory cell by a particular count increment that is based on the time between the writes to the particular memory cell, and determining whether to check a write disturb status of the neighboring memory cell based on the incremented disturb count.

公开(公告)号：US11036593B2

公开(公告)日：2021-06-15

申请号：US16423574

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Justin M. Eno

IPC: G06F11/07 ,  G06F11/14 ,  G06F3/06 ,  G06F1/3225 ,  G06F11/10 ,  G06F11/16

Abstract: The present disclosure includes apparatuses and methods for performing data restore operations in memory. An embodiment includes a memory, and a controller configured to perform a data restore operation on data stored in the memory using a first table and a second table stored in the controller, wherein the first table includes a current mapping of the data stored in the memory that is based on a previous assessment of previous error rates associated with the data stored in the memory, and the second table includes a new mapping of the data stored in the memory that is based on a current assessment of current error rates associated with the data stored in the memory.

公开(公告)号：US20210132689A1

公开(公告)日：2021-05-06

申请号：US16675168

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F3/01 ,  G06K9/00 ,  G02B27/00 ,  G02B27/01 ,  G06F3/0487

Abstract: An apparatus having a wearable structure, a computing device, a display, and a camera. The wearable structure is configured to be worn by a user and can be connected to the computing device, the display, and/or the camera. The computing device can be connected to the wearable structure, the display, and/or the camera. The display can be connected to the wearable structure, the computing device, and/or the camera. The display is configured to provide a graphical user interface (GUI). The camera can be connected to the computing device, the wearable structure, and/or the display. The camera is configured to capture eye movement of the user. A processor in the computing device is configured to identify one or more eye gestures from the captured eye movement. And, the processor is configured to control one or more parameters of the display and/or the GUI based on the identified eye gesture(s).