公开(公告)号：US06480927B1

公开(公告)日：2002-11-12

申请号：US09001592

申请日：1997-12-31

申请人： Mitchell A. Bauman

发明人： Mitchell A. Bauman

IPC分类号： G06F1208

CPC分类号： G06F12/0817 ,  G06F12/0813 ,  G06F13/4022

摘要： A modular, expandable, multi-port main memory system that includes multiple point-to-point switch interconnections and a highly-parallel data path structure that allows multiple memory operations to occur simultaneously. The main memory system includes an expandable number of modular Memory Storage Units, each of which are mapped to a portion of the total address space of the main memory system, and may be accessed simultaneously. Each of the Memory Storage Units includes a predetermined number of memory ports, and an expandable number of memory banks, wherein each of the memory banks may be accessed simultaneously. Each of the memory banks is also modular, and includes an expandable number of memory devices each having a selectable memory capacity. All of the memory devices in the system may be performing different memory read or write operations substantially simultaneously and in parallel. Multiple data paths within each of the Memory Storage Units allow data transfer operations to occur to each of the multiple memory ports in parallel. Simultaneously with the transfer operations occurring to the memory ports, unrelated data transfer operations may occur to multiple ones of the memory devices within all memory banks in parallel. The main memory system further incorporates independent storage devices and control logic to implement a directory-based coherency protocol. Thus the main memory system is adapted to providing the flexibility, bandpass, and memory coherency needed to support a high-speed multiprocessor environment.

摘要翻译： 一种模块化，可扩展的多端口主存储系统，包括多个点对点交换机互连以及允许多个存储器操作同时发生的高度并行数据路径结构。 主存储器系统包括可扩展数量的模块化存储器单元，每个存储单元被映射到主存储器系统的总地址空间的一部分，并且可以被同时访问。 每个存储器存储单元包括预定数量的存储器端口和可扩展数量的存储器组，其中可以同时访问每个存储器组。 每个存储体也是模块化的，并且包括每个具有可选存储器容量的可扩展数量的存储器件。 系统中的所有存储器件可以基本同时并行地执行不同的存储器读或写操作。 每个内存存储单元内的多个数据路径允许数据传输操作并行地发生到多个存储器端口中的每一个。 与存储器端口发生的传送操作同时，并行地在所有存储器组中的多个存储器件中可能发生不相关的数据传输操作。 主存储系统还包括独立的存储设备和控制逻辑，以实现基于目录的一致性协议。 因此，主存储器系统适于提供支持高速多处理器环境所需的灵活性，带通和存储器一致性。

公开(公告)号：US06189078B1

公开(公告)日：2001-02-13

申请号：US09218813

申请日：1998-12-22

申请人： Mitchell A. Bauman ,  Michael L. Haupt

发明人： Mitchell A. Bauman ,  Michael L. Haupt

IPC分类号： G06F1300

CPC分类号： G06F12/0808

摘要： A system and method for reducing data transfer delays in a transaction processing system is provided. The system includes a plurality of devices each having an associated local memory, and a supervisory memory module having a main storage module for storing data segments and a directory storage for maintaining ownership status of each data segment stored in the main storage module and the local memories. A second device makes a request for a data segment which is stored in a first local memory of a first device. A data transfer request for the requested data segment is transferred from the second device to the supervisory memory module, where the data transfer request includes an identifier requesting permission to modify the requested data segment. The requested data and a data transfer response is delivered to the second device upon receipt of the data transfer request, where the data transfer response provides modification privileges of the requested data segment to the second device. A purge command is issued to the first device to invalidate the copy of the requested data segment in the first local memory. Upon issuance of the purge command to the first device, a purge acknowledge response is delivered to the second device, where the purge acknowledge response provides an indication that the copy of the requested data in the first local memory has been invalidated. The second device is prohibited from releasing any modified data until the purge acknowledge response is received.

摘要翻译： 提供了一种用于减少事务处理系统中的数据传输延迟的系统和方法。 该系统包括多个具有相关联的本地存储器的设备，以及具有用于存储数据段的主存储模块和用于维持存储在主存储模块和本地存储器中的每个数据段的所有权状态的目录存储器的监控存储器模块 。 第二设备请求存储在第一设备的第一本地存储器中的数据段。 所请求的数据段的数据传输请求从第二设备传送到监控存储器模块，其中数据传输请求包括请求许可修改所请求的数据段的标识符。 在接收到数据传输请求时，所请求的数据和数据传输响应被传送到第二设备，其中数据传输响应向所述第二设备提供所请求的数据段的修改特权。 向第一设备发出清除命令以使第一本地存储器中所请求的数据段的副本无效。 当向第一设备发出清除命令时，清除确认响应被传递到第二设备，其中清除确认响应提供指示第一本地存储器中所请求的数据的副本已经被无效。 在接收到清除确认响应之前，禁止第二个设备释放任何修改的数据。

公开(公告)号：US6049845A

公开(公告)日：2000-04-11

申请号：US964630

申请日：1997-11-05

申请人： Mitchell A. Bauman ,  Joseph S. Schibinger ,  Donald R. Kalvestrand ,  Douglas E. Morrissey

发明人： Mitchell A. Bauman ,  Joseph S. Schibinger ,  Donald R. Kalvestrand ,  Douglas E. Morrissey

IPC分类号： G06F13/18 ,  G06F12/08 ,  G06F13/16 ,  G06F13/362 ,  G06F15/167 ,  G06F13/00

CPC分类号： G06F13/1605

摘要： A system and method for optimizing the amount of time it takes for a requestor (device) to receive data from a memory storage unit in a multi-requestor bus environment. The present invention provides a unidirectional response signal, referred to as an early warning signal, sent from a memory storage unit to a device, sometime after that device has executed a fetch request for data, to alert the device that the data is forthcoming. This early warning signal allows the device to arbitrate for the data bus so that when the data arrives, the device will have exclusive ownership of the data bus to accept the data immediately. The present invention comprises a main memory, a cache memory, one or more processor modules, one or more I/O modules, and an early warning bus. The cache memory is connected to the main memory via an interface bus. The processor modules are connected to the cache memory via a processor interface bus. The I/O modules are connected to the main memory via an I/O interface bus. Both the processor modules and the I/O modules include means for requesting a data unit from the main memory. The early warning bus is connected between the main memory, the cache memory, and the I/O module.

摘要翻译： 一种用于优化请求者（设备）从多请求者总线环境中的存储器存储单元接收数据所需的时间量的系统和方法。 本发明提供了一种从存储器存储单元发送到设备的称为早期警告信号的单向响应信号，该设备在该设备执行了对数据的取出请求之后的某个时刻向该设备通知数据即将到来。 该预警信号允许设备对数据总线进行仲裁，以便当数据到达时，设备将具有数据总线的独占所有权以立即接受数据。 本发明包括主存储器，高速缓冲存储器，一个或多个处理器模块，一个或多个I / O模块和预警总线。 高速缓存通过接口总线连接到主存储器。 处理器模块通过处理器接口总线连接到高速缓冲存储器。 I / O模块通过I / O接口总线连接到主存储器。 处理器模块和I / O模块都包括用于从主存储器请求数据单元的装置。 预警总线连接在主存储器，高速缓冲存储器和I / O模块之间。

公开(公告)号：US5946710A

公开(公告)日：1999-08-31

申请号：US748772

申请日：1996-11-14

申请人： Mitchell A. Bauman ,  Donald C. Englin

发明人： Mitchell A. Bauman ,  Donald C. Englin

IPC分类号： G06F12/08

CPC分类号： G06F12/0864 ,  G06F12/0851

摘要： Method and apparatus for maximizing cache memory throughput in a system where a plurality of requesters may contend for access to a same memory simultaneously. The memory utilizes an interleaved addressing scheme wherein each memory segment is associated with a separate queuing structure and the memory is mapped noncontiguously within the same segment so that all segments are accessed equally. Throughput is maximized as the plurality of requesters are queued evenly throughout the system.

摘要翻译： 用于在多个请求者可能竞争同时访问相同存储器的系统中最大化高速缓冲存储器吞吐量的方法和装置。 存储器利用交错寻址方案，其中每个存储器段与单独的排队结构相关联，并且存储器被不连续地映射在相同的段内，使得所有段被平等地访问。 吞吐量最大化，因为多个请求者在整个系统中均匀排队。

公开(公告)号：US5875462A

公开(公告)日：1999-02-23

申请号：US579897

申请日：1995-12-28

申请人： Mitchell A. Bauman ,  Donald C. Englin ,  Mark L. Balding

发明人： Mitchell A. Bauman ,  Donald C. Englin ,  Mark L. Balding

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0811 ,  G06F12/0813 ,  G06F12/0822

摘要： A cache architecture for a multiprocessor data processing system. The cache architecture includes multiple first-level caches, two second-level caches, and main storage that is addressable by each of the processors. Each first-level cache is dedicated to a respective one of the processors. Each of the second-level caches is coupled to the other second-level cache, coupled to the main storage, and coupled to predetermined ones of the first-level caches. The range of cacheable addresses for both of the second-level caches encompasses the entire address space of the main storage. Each of the second-level caches may be viewed as dedicated for write access to the set of processors associated with the predetermined set of first-level caches, and shared for read access to the other set of processors. The dedicated and shared nature enhances system efficiency. The cache architecture includes coherency control that filters invalidation traffic between the second-level caches. The filtering of invalidation traffic enhances system efficiency and is accomplished by tracking which second-level cache has the most recent version of the cached data.

摘要翻译： 用于多处理器数据处理系统的高速缓存架构。 缓存架构包括多个第一级高速缓存，两个二级高速缓存和可由每个处理器寻址的主存储器。 每个第一级缓存专用于相应的一个处理器。 每个第二级高速缓存耦合到另一个二级高速缓存，耦合到主存储器，并且耦合到第一级高速缓存中的预定的高速缓存。 二级缓存的可缓存地址的范围包括主存储器的整个地址空间。 每个二级高速缓存可以被视为专用于对与预定的一级高速缓存集合相关联的一组处理器的写入访问，并且被共享用于对另一组处理器的读取访问。 专用和共享的性质提高了系统效率。 缓存体系结构包括一致性控制，用于过滤二级缓存之间的无效流量。 无效流量的过滤增强了系统效率，并且通过跟踪哪个二级缓存具有最新版本的缓存数据来实现。

公开(公告)号：US5875201A

公开(公告)日：1999-02-23

申请号：US777037

申请日：1996-12-30

申请人： Mitchell A. Bauman ,  Donald W. Mackenthun ,  Gary J. Lucas ,  James L. Federici

发明人： Mitchell A. Bauman ,  Donald W. Mackenthun ,  Gary J. Lucas ,  James L. Federici

IPC分类号： G06F11/10 ,  G06F11/00 ,  G11C29/00

CPC分类号： G06F11/1008 ,  G06F11/1064

摘要： Method and apparatus for detecting and correcting memory storage data errors in a system utilizing parity error detection. An error detected in the memory storage device results in a parity error being reported, thereby causing the corresponding address location to be deactivated. Once deactivated, no further reading or writing is performed at that address location for a predetermined time period. The parity error reporting and address deactivation is accomplished without an access time penalty and requires a reduced number of I/O pins.

摘要翻译： 用于检测和校正使用奇偶校验错误检测的系统中的存储器存储数据错误的方法和装置。 在存储器存储装置中检测到的错误导致正在报告奇偶校验错误，从而导致对应的地址位置被去激活。 一旦停用，在该地址位置不进行进一步的读取或写入达预定的时间段。 奇偶校验错误报告和地址禁用在没有访问时间损失的情况下完成，并且需要减少I / O引脚数。

公开(公告)号：US4596977A

公开(公告)日：1986-06-24

申请号：US677126

申请日：1984-12-03

申请人： Mitchell A. Bauman ,  David C. Ullestad

发明人： Mitchell A. Bauman ,  David C. Ullestad

IPC分类号： H03M1/00

CPC分类号： H03M1/1095 ,  H03M1/52

摘要： A control method and apparatus for dual slope analog to digital signal conversion is disclosed in which the time required for input signal integration is sensed. A switch connected across the integrator is closed in response to sensing of an integration time which exceeds the integration interval corresponding to a limit of the expected range of input signal values.

摘要翻译： 公开了一种用于双斜率模数转换的控制方法和装置，其中检测输入信号积分所需的时间。 连接在积分器两端的开关响应于积分时间的检测而被闭合，积分时间超过对应于输入信号值的期望范围的限制的积分间隔。

公开(公告)号：US07634709B2

公开(公告)日：2009-12-15

申请号：US09972490

申请日：2001-10-05

申请人： Mitchell A. Bauman ,  Eugene A. Rodi

发明人： Mitchell A. Bauman ,  Eugene A. Rodi

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： G06F11/1044

摘要： Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. It uses ×4 bit DRAM devices organized in a code word of 128 data bit words and 16 check bits. These 16 check bits are generated in such a way as to provide a code capable of 4 bit adjacent error correction within a family (i.e., in a ×4 DRAM) and double bit non-adjacent error detection across the entire 128 bit word, with single bit correction across the word as well. Each device can be thought of as a separate family of bits, errors occurring in more than one family are not correctable, but may be detected if only one bit in each of two families is in error. Syndrome generation and regeneration are used together with a specific large code word. Decoding the syndrome and checking it against the regenerated syndrome yield data sufficient for providing the features described.

摘要翻译： 与DRAM芯片故障相关的错误校正和错误检测，特别是适配的服务器内存子系统。 它使用组织在128个数据位字和16个校验位的代码字中的x4位DRAM器件。 这16个校验位的生成方式是提供一个能够在一个系列内进行4位相邻纠错的代码（即，在x4 DRAM中）和跨整个128位字的双位非相邻错误检测的代码，其中单个 同时也纠正了这个词。 每个设备都可以被认为是一个独立的位系列，发生在多个系列中的错误是不可校正的，但是如果两个系列中的每一个中只有一位是错误的，则可能被检测到。 综合征生成和再生与特定的大码字一起使用。 对该综合征进行解码并针对再生综合征进行检查，产生足以提供所述特征的数据。

公开(公告)号：US07277825B1

公开(公告)日：2007-10-02

申请号：US10423100

申请日：2003-04-25

申请人： Marwan A. Orfali ,  Mitchell A. Bauman ,  Myoungran Kim

发明人： Marwan A. Orfali ,  Mitchell A. Bauman ,  Myoungran Kim

IPC分类号： G06F11/30

CPC分类号： G06F11/3414 ,  G06F11/3452

摘要： An improved system and method for completing performance analysis for a target system is disclosed. According to the current invention, different types of configurations files are created, each to describe one or more respective aspects and/or portions of the target system. Each of these file types may include a combination of parameter values and equations that represent the respective portion of the system. After the configuration files are defined, scenarios are created. Each scenario includes a set of configuration files, with some or all of the files being of different file types. The files included within a scenario provide all parameter values and equations needed to calculate performance data for a particular revision of the target system. Next, a performance study is defined to include one or more of the scenarios. Finally, performance data is derived for each of the scenarios in the performance study.

摘要翻译： 公开了用于完成目标系统的性能分析的改进的系统和方法。 根据本发明，创建不同类型的配置文件，每个配置文件描述目标系统的一个或多个相应方面和/或部分。 这些文件类型中的每一个可以包括表示系统的相应部分的参数值和等式的组合。 定义配置文件后，将创建方案。 每个场景包括一组配置文件，其中一些或全部文件是不同的文件类型。 场景中包含的文件提供了计算目标系统特定版本的性能数据所需的所有参数值和方程式。 接下来，性能研究被定义为包括一个或多个场景。 最后，在性能研究中为每个场景导出性能数据。

公开(公告)号：US07032079B1

公开(公告)日：2006-04-18

申请号：US10318678

申请日：2002-12-13

申请人： Mitchell A. Bauman ,  R. Lee Gilbertson ,  Jerome G. Carlin

发明人： Mitchell A. Bauman ,  R. Lee Gilbertson ,  Jerome G. Carlin

IPC分类号： G06F12/00

CPC分类号： G06F12/0817

摘要： A system and method for managing memory data within a data processing system is disclosed. A main memory is provided to store data signals. When the main memory receives a request to read data signals, the main memory determines whether an updated copy of the requested data signals may be stored within some other storage device within the system. If so, the main memory issues a snoop request to this other storage device to cause any updated copy of the requested data to be returned to the main memory. In addition, the main memory reads the requested data signals from its data store. This data will be used to satisfy the read request if an updated copy of the data signals is not returned to the main memory in response to the snoop request. Otherwise, the updated copy is provided to fulfill the request.

摘要翻译： 公开了一种用于管理数据处理系统内的存储器数据的系统和方法。 提供主存储器来存储数据信号。 当主存储器接收到读取数据信号的请求时，主存储器确定所请求的数据信号的更新副本是否可以存储在系统内的其它存储设备内。 如果是这样，主存储器向这个其他存储设备发出窥探请求，以使所请求的数据的任何更新的副本被返回到主存储器。 此外，主存储器从其数据存储器读取所请求的数据信号。 如果数据信号的更新副本不响应于窥探请求返回主存储器，则该数据将用于满足读请求。 否则，提供更新的副本以满足请求。