公开(公告)号：US06455376B1

公开(公告)日：2002-09-24

申请号：US09874455

申请日：2001-06-05

申请人： Tso Hung Fan ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Tso Hung Fan ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory is disclosed. The method begins a stacked gate on the substrate. A shallow junction doping is performed on a substrate having a stacked gate already formed thereon, with the stacked gate serving as a mask, so as to form a shallow junction doped region in the substrate adjacent to both sides of the stacked gate. A mask layer is formed on the substrate to cover a top surface and sidewalls of the stacked gate, while exposing portions of the shallow junction doped region. With the mask layer serving as a mask, a deep junction doping is performed on the substrate to form a deep junction doped region in the substrate adjacent to both sides of the mask layer. After the mask layer is removed, a thermal process is performed to form a source/drain region having both the shallow junction doped region and deep junction doped region.

摘要翻译： 公开了一种制造闪速存储器的方法。 该方法在衬底上开始堆叠栅极。 在其上已经形成有堆叠栅极的衬底上执行浅结掺杂，其中堆叠的栅极用作掩模，以便在与栅极的两侧相邻的衬底中形成浅结掺杂区域。 掩模层形成在衬底上以覆盖堆叠栅极的顶表面和侧壁，同时暴露浅结掺杂区域的部分。 在掩模层用作掩模的情况下，在衬底上进行深结掺杂以在衬底中邻近掩模层的两侧形成深结掺杂区域。 在去除掩模层之后，执行热处理以形成具有浅结掺杂区域和深掺杂区域的源极/漏极区域。

公开(公告)号：US07031196B2

公开(公告)日：2006-04-18

申请号：US10757073

申请日：2004-01-14

申请人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： G11C16/00

CPC分类号： G11C16/0475 ,  G11C16/3468 ,  H01L21/28273 ,  H01L29/792 ,  H01L29/7923

摘要： A method of programming the memory cell comprises setting the memory cell to an initial state of a first gate threshold voltage, performing a processing sequence including: applying a voltage bias between the gate and the first junction region to cause electric hole to migrate towards and be retained in the trapping layer, and evaluating a read current generated in response to the voltage bias to determine whether a second gate threshold voltage is reached, wherein the second gate threshold voltage is lower than the first gate threshold voltage. The processing sequence is repeated a number of times by varying one or more time the voltage bias between the gate and the first junction region until the second gate threshold voltage is reached and the memory cell is in a program state.

摘要翻译： 一种对存储器单元进行编程的方法包括将存储单元设置为第一栅极阈值电压的初始状态，执行处理顺序，包括：在栅极与第一结区域之间施加电压偏置，使电孔朝向 保持在捕获层中，并且评估响应于电压偏置产生的读取电流，以确定是否达到第二栅极阈值电压，其中第二栅极阈值电压低于第一栅极阈值电压。 通过改变栅极和第一结区域之间的电压偏压的一个或多个时间直到达到第二栅极阈值电压并且存储器单元处于编程状态来重复处理顺序多次。

公开(公告)号：US06914819B2

公开(公告)日：2005-07-05

申请号：US10653892

申请日：2003-09-04

申请人： Chih-Chieh Yeh ,  Hung-Yueh Chen ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Hung-Yueh Chen ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/0475 ,  G11C16/26

摘要： A method of operating a non-volatile memory cell, wherein the non-volatile memory cell includes a word line, a first bit line, and a second bit line, the method includes programming the memory cell that includes applying a high positive bias to the first bit line, applying a ground bias to the second bit line, and applying a high negative bias to the word line, wherein positively-charged holes tunnel through the dielectric layer into the trapping layer.

摘要翻译： 一种操作非易失性存储单元的方法，其中所述非易失性存储单元包括字线，第一位线和第二位线，所述方法包括对所述存储器单元进行编程，所述存储单元包括向所述存储单元施加高正偏压 第一位线，对第二位线施加接地偏置，以及向字线施加高负偏压，其中带正电荷的空穴穿过介电层进入捕获层。

公开(公告)号：US06801453B2

公开(公告)日：2004-10-05

申请号：US10112871

申请日：2002-04-02

申请人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： G11C1604

CPC分类号： G11C16/3418 ,  G11C16/0475 ,  G11C16/26

摘要： A method of a read scheme for a non-volatile memory cell. The non-volatile memory cell includes a substrate, a source, a drain and a gate above a channel separated by a nonconducting charge trapping material sandwiched between first and second insulating layers. The method applies a first positive drain-to-source bias, a second positive source-to-substrate bias, and a third positive gate-to-source bias to read the source-side charges trapped in the trapping material near the source side.

摘要翻译： 一种用于非易失性存储单元的读取方案的方法。 非易失性存储单元包括衬底，源极，漏极以及由夹在第一绝缘层和第二绝缘层之间的非导电电荷捕获材料隔开的沟道之上的栅极。 该方法应用第一正的漏极 - 源极偏置，第二正的源极 - 衬底偏置和第三正向栅极 - 源偏置来读取在源极附近的捕获材料中的源极电荷。

公开(公告)号：US06657894B2

公开(公告)日：2003-12-02

申请号：US10112923

申请日：2002-03-29

申请人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： G11C1604

CPC分类号： G11C16/0491 ,  G11C16/12

摘要： A virtual ground nonvolatile memory cell array is formed by a plurality of adjacent nonvolatile memory cells arranged in rows and columns so as to form an array. Each of the nonvolatile memory cells is formed by an N channel MOSFET with a trapping layer formed between two isolating layers. In the erase state, the trapping layer stores an amount of electrons. A method for programming the virtual ground nonvolatile memory cell array is also disclosed. The potentials applied to the bitlines and wordlines in the array are preset to program nonvolatile memory cells and not to disturb cells adjacent to the nonvolatile memory cell to be programmed.

摘要翻译： 由布置成行和列的多个相邻的非易失性存储单元形成虚拟非易失性存储单元阵列，以形成阵列。 每个非易失性存储单元由具有在两个隔离层之间形成的捕获层的N沟道MOSFET形成。 在擦除状态下，捕获层存储一定量的电子。 还公开了一种用于编程虚拟接地非易失性存储单元阵列的方法。 应用于阵列中的位线和字线的电位被预设为非易失性存储器单元，而不是干扰与待编程的非易失性存储器单元相邻的单元。

公开(公告)号：US06822910B2

公开(公告)日：2004-11-23

申请号：US10248220

申请日：2002-12-29

申请人： Wen-Jer Tsai ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Wen-Jer Tsai ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C1604

CPC分类号： G11C16/10 ,  G11C16/0466

摘要： A non-volatile memory device is described, comprising a plurality of memory cells, a plurality of word lines, a plurality of drain lines, and a plurality of source lines, wherein two adjacent memory cells in a column constitute a cell pair, and all cell pairs are arranged in rows and columns. The two memory cells in each cell pair share a source region, and two adjacent cell pairs in a column share a drain region. The source regions and the gates of the memory cells in the same row are coupled to a source line and a word line, respectively, and the drain regions of the memory cells in the same column are coupled to a drain line.

摘要翻译： 描述了一种非易失性存储器件，其包括多个存储器单元，多个字线，多个漏极线和多个源极线，其中列中的两个相邻的存储器单元构成一个单元对，并且全部 单元对以行和列排列。 每个单元对中的两个存储单元共享源区，并且列中的两个相邻单元对共享漏区。 相同行中的存储单元的源极区域和栅极分别耦合到源极线和字线，并且同一列中的存储器单元的漏极区域耦合到漏极线。

公开(公告)号：US06646924B1

公开(公告)日：2003-11-11

申请号：US10064642

申请日：2002-08-02

申请人： Wen-Jer Tsai ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Wen-Jer Tsai ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C1604

CPC分类号： H01L29/7885 ,  G11C16/0475 ,  H01L27/115

摘要： A non-volatile memory is described, which comprises a plurality of memory cells, a plurality of word lines, a plurality of drain lines and a plurality of source lines. Two adjacent memory cells in the same row share a source and are grouped into a cell pair, and all of the cell pairs are arranged in rows and columns, wherein two cell pairs in the same row share a drain. The sources of the memory cells in the same row are connected to a source line, and the drains of the memory cells in the same row are connected to a drain line. The gates of the memory cells in the same column are coupled to a word line.

摘要翻译： 描述了一种非易失性存储器，其包括多个存储器单元，多个字线，多个漏极线和多个源极线。 同一行中的两个相邻的存储单元共享一个源并将其分组成一个单元对，并且所有的单元对排列成行和列，其中同一行中的两个单元对共享一个漏极。 同一行中的存储单元的源极连接到源极线，并且同一行中的存储器单元的漏极连接到漏极线。 同一列中的存储单元的栅极耦合到字线。

公开(公告)号：US06614694B1

公开(公告)日：2003-09-02

申请号：US10112707

申请日：2002-04-02

申请人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： G11C1604

CPC分类号： G11C16/3404 ,  A61K31/365 ,  G11C16/0475 ,  G11C16/3418

摘要： A method of an erase scheme for a non-volatile memory cell. The non-volatile memory cell includes a substrate, source, drain with a channel region and a gate above the channel region separated by nonconducting charge-trapping material sandwiched between first and second insulating layers. The method includes the following steps. First, hot hole erase is performed to inject hot holes into the nonconducting charge-trapping material to eliminate first electrons trapped in the nonconducting charge-trapping material and causing some holes to remain in the second insulating layer. Finally, soft anneal is performed to inject second electrons to the second insulating layer to eliminate the holes left in the second insulating layer.

摘要翻译： 一种用于非易失性存储单元的擦除方案的方法。 非易失性存储单元包括具有沟道区的衬底，源极，漏极以及夹在第一和第二绝缘层之间的由不导电的电荷俘获材料隔开的沟道区上方的栅极。 该方法包括以下步骤。 首先，进行热孔擦除以将热空穴注入到不导电的电荷捕获材料中，以消除捕获在不导电的电荷捕获材料中的第一电子，并使一些孔留在第二绝缘层中。 最后，进行软退火以将第二电子注入第二绝缘层以消除留在第二绝缘层中的孔。

公开(公告)号：US06882575B2

公开(公告)日：2005-04-19

申请号：US10790994

申请日：2004-03-01

申请人： Wen-Jer Tsai ,  Chih-Chieh Yeh ,  Tao-Cheng Lu ,  Samuel C. Pan

发明人： Wen-Jer Tsai ,  Chih-Chieh Yeh ,  Tao-Cheng Lu ,  Samuel C. Pan

IPC分类号： G11C16/14 ,  G11C7/00

CPC分类号： G11C16/14

摘要： An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.

摘要翻译： 提供了一种用于非易失性存储器的存储单元的擦除方法。 每个存储单元包括栅极，源极，漏极，电子俘获层和衬底。 通过向控制栅极施加第一电压，向源施加第二电压，向漏极施加第三电压并向衬底施加第四电压来擦除存储单元内的数据。 通过负栅极F-N隧道效应将电子从电子捕获层拉入沟道。

公开(公告)号：US20050052228A1

公开(公告)日：2005-03-10

申请号：US10653892

申请日：2003-09-04

申请人： Chih-Chieh Yeh ,  Hung-Yueh Chen ,  Wen-Jar Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Hung-Yueh Chen ,  Wen-Jar Tsai ,  Tao-Cheng Lu

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H03F3/38

CPC分类号： G11C16/3418 ,  G11C16/0475 ,  G11C16/26

摘要： A method of operating a non-volatile memory cell, wherein the non-volatile memory cell includes a word line, a first bit line, and a second bit line, the method includes programming the memory cell that includes applying a high positive bias to the first bit line, applying a ground bias to the second bit line, and applying a high negative bias to the word line, wherein positively-charged holes tunnel through the dielectric layer into the trapping layer.