公开(公告)号：US08450777B2

公开(公告)日：2013-05-28

申请号：US12778751

申请日：2010-05-12

Applicant: Munaf Rahimo ,  Jan Vobecky ,  Arnost Kopta

Inventor： Munaf Rahimo ,  Jan Vobecky ,  Arnost Kopta

IPC: H01L29/66

CPC classification number: H01L29/7395 ,  H01L21/266 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66333

Abstract: A reverse-conducting insulated gate bipolar transistor includes a wafer of first conductivity type with a second layer of a second conductivity type and a third layer of the first conductivity type. A fifth electrically insulating layer partially covers these layers. An electrically conductive fourth layer is electrically insulated from the wafer by the fifth layer. The third through the fifth layers form a first opening above the second layer. A sixth layer of the second conductivity type and a seventh layer of the first conductivity type are arranged alternately in a plane on a second side of the wafer. A ninth layer is formed by implantation of ions through the first opening using the fourth and fifth layers as a first mask.

Abstract translation: 反向导通绝缘栅双极晶体管包括具有第二导电类型的第二层和第一导电类型的第三层的第一导电类型的晶片。 第五电绝缘层部分地覆盖这些层。 导电的第四层通过第五层与晶片电绝缘。 第三至第五层在第二层上形成第一开口。 第二导电类型的第六层和第一导电类型的第七层交替地布置在晶片的第二侧上的平面中。 通过使用第四和第五层作为第一掩模通过第一开口注入离子形成第九层。

公开(公告)号：US08324062B2

公开(公告)日：2012-12-04

申请号：US12635975

申请日：2009-12-11

Applicant: Arnost Kopta ,  Munaf Rahimo

Inventor： Arnost Kopta ,  Munaf Rahimo

IPC: H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395

Abstract: A method of manufacturing a power semiconductor device is provided. A first oxide layer is produced on a first main side of a substrate of a first conductivity type. A structured gate electrode layer with at least one opening is then formed on the first main side on top of the first oxide layer. A first dopant of the first conductivity type is implanted into the substrate on the first main side using the structured gate electrode layer as a mask, and the first dopant is diffused into the substrate. A second dopant of a second conductivity type is then implanted into the substrate on the first main side, and the second dopant is diffused into the substrate. After diffusing the first dopant into the substrate and before implanting the second dopant into the substrate, the first oxide layer is partially removed. The structured gate electrode layer can be used as a mask for implanting the second dopant.

Abstract translation: 提供一种制造功率半导体器件的方法。 在第一导电类型的基板的第一主侧上产生第一氧化物层。 然后在第一氧化物层的顶部的第一主侧上形成具有至少一个开口的结构化的栅极电极层。 使用结构化栅极电极层作为掩模，将第一导电类型的第一掺杂剂注入到第一主侧的衬底中，并且第一掺杂剂扩散到衬底中。 然后将第二导电类型的第二掺杂剂注入到第一主侧上的衬底中，并且将第二掺杂剂扩散到衬底中。 在将第一掺杂剂扩散到衬底中并且在将第二掺杂剂注入衬底之前，部分地去除第一氧化物层。 结构化栅极电极层可以用作用于注入第二掺杂剂的掩模。

公开(公告)号：US20080087947A1

公开(公告)日：2008-04-17

申请号：US11979454

申请日：2007-11-02

Applicant: Munaf Rahimo

Inventor： Munaf Rahimo

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/0696 ,  H01L29/7395

Abstract: An n-channel insulated gate semiconductor device with an active cell (5) comprising a p channel well region (6) surrounded by an n type third layer (8), the device further comprising additional well regions (11) formed adjacent to the channel well region (6) outside the active semiconductor cell (5) has enhanced safe operating are capability. The additional well regions (11) outside the active cell (5) do not affect the active cell design in terms of cell pitch, i.e. the design rules for cell spacing, and hole drainage between the cells, hence resulting in optimum carrier profile at the emitter side for low on-state losses.

Abstract translation: 一种具有活动电池（5）的n沟道绝缘栅极半导体器件，包括由n型第三层（8）围绕的ap沟道阱区（6），该器件还包括邻近沟道阱形成的附加阱区（11） 活性半导体电池（5）外部的区域（6）具有增强的安全运行能力。 在活性细胞（5）外部的附加阱区（11）在细胞间距方面不影响活性细胞设计，即细胞间隔的设计规则和细胞之间的孔引流，因此导致最佳的载体谱 发射极侧为低导通状态损耗。

公开(公告)号：US20060022261A1

公开(公告)日：2006-02-02

申请号：US10537834

申请日：2003-12-09

Applicant: Munaf Rahimo ,  Christoph Von Arx

Inventor： Munaf Rahimo ,  Christoph Von Arx

IPC: H01L29/76 ,  H01L21/8238

CPC classification number: H01L29/0696 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/4238 ,  H01L29/6634 ,  H01L29/7396

Abstract: The invention relates to a manufacturing method for an insulated gate semiconductor device cell, comprising the steps of forming a cell window (3) in a layered structure that is located on top of a semiconductor substrate (1), forming at least one process mask that partially covers the cell window (3). In forming the cell window (3), at least one strip (41, 42) of the layered structure is left to remain inside the cell window (3) and at least one strip (41, 42) is used to serve as an edge for the at least one process mask (51, 52). The invention further relates to an insulated gate semiconductor device, comprising a semiconductor substrate (1) having an essentially planar top surface and an insulated gate formed on the top surface by a layered structure (2) that comprises at least one electrically insulating layer (22), wherein at least one strip (41, 42) of the layered structure (2) is disposed on a third area of the top surface between an edge of the insulated gate and a first main contact (6).

Abstract translation: 本发明涉及一种用于绝缘栅半导体器件单元的制造方法，包括以下步骤：形成位于半导体衬底（1）顶部上的分层结构中的电池窗（3），形成至少一个工艺掩模， 部分地覆盖单元窗口（3）。 在形成电池窗（3）时，分层结构的至少一个条（41,42）留在电池窗（3）内，并且至少一个条（41,42）用作边缘 用于所述至少一个处理掩模（51,52）。 本发明还涉及一种绝缘栅极半导体器件，其包括具有基本上平坦的顶表面的半导体衬底（1）和通过层状结构（2）在顶表面上形成的绝缘栅极，所述层状结构（2）包括至少一个电绝缘层（22 ），其中所述层状结构（2）的至少一个条带（41,42）设置在所述绝缘栅极的边缘和第一主触头（6）之间的所述顶表面的第三区域上。