公开(公告)号：US20140320178A1

公开(公告)日：2014-10-30

申请号：US14358103

申请日：2011-11-22

Applicant: Falah Hosini ,  Madhan Mohan ,  Siva Nagi Reddy Pamulapati ,  Arnost Kopta ,  Munaf Rahimo ,  Raffael Schnell ,  Ulrich Schlapbach

Inventor： Falah Hosini ,  Madhan Mohan ,  Siva Nagi Reddy Pamulapati ,  Arnost Kopta ,  Munaf Rahimo ,  Raffael Schnell ,  Ulrich Schlapbach

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K17/08128 ,  H03K17/0828 ,  H03K17/18 ,  H03K17/567 ,  H03K2217/0027 ,  H03K2217/0036

Abstract: A reverse-conducting insulated gate bipolar transistor, particularly a bi-mode insulated gate transistor, is controlled by responding to an ON command by applying high-level gate voltage for a first period, during which a current is fed into a connection point, from which it flows either through the RC-IGBT or along a different path. Based hereon, it is determined whether the RC-IGBT conducts in its forward/IGBT or reverse/diode mode, and the RC-IGBT is either driven at high or low gate voltage. Subsequent conduction mode changes may be monitored in the same way, and the gate voltage may be adjusted accordingly. A special turn-off procedure may be applied in response to an OFF command in cases where the RC-IGBT conducts in the reverse mode, wherein a high-level pulse is applied for a second period before the gate voltage goes down to turn-off level.

Abstract translation: 反向导通的绝缘栅双极晶体管，特别是双模绝缘栅极晶体管，通过在第一周期内施加高电平栅极电压来响应于ON命令来控制，在此期间，电流被馈送到连接点 其通过RC-IGBT或沿着不同的路径流动。 基于此，确定RC-IGBT是在其正向/ IGBT还是反向/二极管模式下导通，并且RC-IGBT是以高或低栅极电压驱动的。 可以以相同的方式监视随后的传导模式改变，并且可以相应地调整栅极电压。 在RC-IGBT以反向模式导通的情况下，可以响应于OFF命令来应用特殊的关断过程，其中在栅极电压下降至关断之前的第二周期施加高电平脉冲 水平。

公开(公告)号：US08823052B2

公开(公告)日：2014-09-02

申请号：US13530727

申请日：2012-06-22

Applicant: Munaf Rahimo

Inventor： Munaf Rahimo

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/08 ,  H01L29/74 ,  H01L29/744

CPC classification number: H01L29/74 ,  H01L29/0839 ,  H01L29/102 ,  H01L29/744

Abstract: A power semiconductor device includes a four-layer structure having layers arranged in order: (i) a cathode layer of a first conductivity type with a central area being surrounded by a lateral edge, the cathode layer being in direct electrical contact with a cathode electrode, (ii) a base layer of a second conductivity type, (iii) a drift layer of the first conductivity typehaving a lower doping concentration than the cathode layer, and (iv) an anode layer of the second conductivity type which is in electrical contact with an anode electrode. The base layer includes a first layer as a continuous layer contacting the central area of the cathode layer. A resistance reduction layer, in which the resistance at the junction between the lateral edge of the cathode and base layers is reduced, is arranged between the first layer and the cathode layer and covers the lateral edge of the cathode layer.

Abstract translation: 功率半导体器件包括具有顺序布置的层的四层结构：（i）第一导电类型的阴极层，其中心区域被侧边缘包围，阴极层与阴极电极直接电接触 ，（ii）第二导电类型的基底层，（iii）第一导电类型的漂移层具有比阴极层更低的掺杂浓度，以及（iv）第二导电类型的与电接触的阳极层 与阳极电极。 基层包括作为与阴极层的中心区域接触的连续层的第一层。 阴极和底层的侧边缘之间的接合处的电阻减小的电阻降低层被布置在第一层和阴极层之间并且覆盖阴极层的侧边缘。

公开(公告)号：US08501548B2

公开(公告)日：2013-08-06

申请号：US12951334

申请日：2010-11-22

Applicant: Jan Vobecky ,  Munaf Rahimo

Inventor： Jan Vobecky ,  Munaf Rahimo

IPC: H01L21/332

CPC classification number: H01L21/26513 ,  H01L21/268 ,  H01L29/0834 ,  H01L29/66333

Abstract: A method for producing a semiconductor device such as a RC-IGBT or a BIGT having a patterned surface wherein partial regions doped with dopants of a first conductivity type and regions doped with dopants of a second conductivity type are on a same side of a semiconductor substrate is proposed. An exemplary method includes: (a) implanting dopants of the first conductivity type and implanting dopants of the second conductivity type into the surface to be patterned; (b) locally activating dopants of the first conductivity type by locally heating the partial region of the surface to be patterned to a first temperature (e.g., between 900 and 1000° C.) using a laser beam similar to those used in laser annealing; and (c) activating the dopants of the second conductivity type by heating the substrate to a second temperature lower than the first temperature (e.g., to a temperature below 600° C.). Boron is an exemplary dopant of the first conductivity type, and phosphorous is an exemplary dopant of the second conductivity type. Boron can be activated in the regions irradiated only with the laser beam, whereas phosphorus may be activated in a low temperature sintering step on the entire surface.

Abstract translation: 一种用于制造具有图案化表面的诸如RC-IGBT或BIGT的半导体器件的方法，其中掺杂有第一导电类型的掺杂剂的部分区域和掺杂有第二导电类型的掺杂剂的区域在半导体衬底的同一侧 被提出。 一种示例性方法包括：（a）将第一导电类型的掺杂剂注入并将第二导电类型的掺杂剂注入到待图案化的表面中; （b）通过使用类似于激光退火中使用的激光束局部加热要构图的表面的部分区域到第一温度（例如在900和1000℃之间）来局部地激活第一导电类型的掺杂剂; 和（c）通过将衬底加热到​​低于第一温度的第二温度（例如，温度低于600℃）来激活第二导电类型的掺杂剂。 硼是第一导电类型的示例性掺杂剂，磷是第二导电类型的示例性掺杂剂。 可以在仅用激光束照射的区域中激活硼，而磷可以在整个表面上的低温烧结步骤中活化。

公开(公告)号：US08415239B2

公开(公告)日：2013-04-09

申请号：US12731977

申请日：2010-03-25

Applicant: Jan Vobecky ,  Munaf Rahimo

Inventor： Jan Vobecky ,  Munaf Rahimo

IPC: H01L21/22 ,  H01L21/225 ,  H01L21/265

CPC classification number: H01L21/221 ,  H01L21/26506 ,  H01L21/266

Abstract: An exemplary method is disclosed for manufacturing a power semiconductor device which has a first electrical contact on a first main side and a second electrical contact on a second main side opposite the first main side and at least a two-layer structure with layers of different conductivity types, and includes providing an n-doped wafer and creating a surface layer of palladium particles on the first main side. The wafer is irradiated on the first main side with ions. Afterwards, the palladium particles are diffused into the wafer at a temperature of not more than 750° C., by which diffusion a first p-doped layer is created. Then, the first and second electrical contacts are created. At least the irradiation with ions is performed through a mask.

Abstract translation: 公开了一种用于制造功率半导体器件的示例性方法，该功率半导体器件在第一主侧具有第一电接触，而在与第一主侧相对的第二主侧上具有第二电接触，以及至少具有不同导电层的两层结构 类型，并且包括提供n掺杂晶片并在第一主侧上产生钯颗粒的表面层。 用离子将晶片照射在第一主面上。 之后，钯粒子在不超过750℃的温度下扩散到晶片中，由此产生第一p掺杂层的扩散。 然后，产生第一和第二电触点。 至少通过掩模进行离子照射。

公开(公告)号：US20110204414A1

公开(公告)日：2011-08-25

申请号：US13098827

申请日：2011-05-02

Applicant: Arnost KOPTA ,  Munaf Rahimo

Inventor： Arnost KOPTA ,  Munaf Rahimo

IPC: H01L29/739

CPC classification number: H01L29/7395 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7397

Abstract: A reverse-conducting semiconductor device includes a freewheeling diode and an insulated gate bipolar transistor (IGBT) on a common wafer. Part of the wafer forms a base layer with a base layer thickness. The IGBT includes a collector side and an emitter side arranged on opposite sides of the wafer. A first layer of a first conductivity type and a second layer of a second conductivity type are alternately arranged on the collector side. The first layer includes at least one first region with a first region width and at least one first pilot region with a first pilot region width. The second layer includes at least one second region with a second region width and at least one second pilot region with a second pilot region width. Each second region width is equal to or larger than the base layer thickness, whereas each first region width is smaller than the base layer thickness. Each second pilot region width is larger than each first pilot region width. Each first pilot region width is equal to or larger than two times the base layer thickness, and the sum of the areas of the second pilot regions is larger than the sum of the areas of the first pilot regions.

Abstract translation: 反向导电半导体器件包括在同一晶片上的续流二极管和绝缘栅双极晶体管（IGBT）。 晶片的一部分形成具有基层厚度的基底层。 IGBT包括布置在晶片的相对侧上的集电极侧和发射极侧。 第一导电类型的第一层和第二导电类型的第二层交替地布置在集电极侧。 第一层包括具有第一区域宽度的至少一个第一区域和具有第一引导区域宽度的至少一个第一引导区域。 第二层包括具有第二区域宽度的至少一个第二区域和具有第二导频区域宽度的至少一个第二导频区域。 每个第二区域宽度等于或大于基底层厚度，而每个第一区域宽度小于基底层厚度。 每个第二导频区宽度大于每个第一导频区宽度。 每个第一导频区宽度等于或大于基层厚度的两倍，并且第二导频区域的面积之和大于第一导频区域的面积之和。

公开(公告)号：US20080164490A1

公开(公告)日：2008-07-10

申请号：US12007890

申请日：2008-01-16

Applicant: Munaf Rahimo ,  Peter Streit

Inventor： Munaf Rahimo ,  Peter Streit

IPC: H01L29/745 ,  H01L21/332

CPC classification number: H01L29/102 ,  H01L29/744

Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.

Abstract translation: 具有四层npnp结构的功率半导体器件可以通过栅电极截止。 第一基极层包括与阴极区域相邻的阴极基极区域和与栅极电极相邻但与阴极区域相距一定距离的栅极基极区域。 栅极基极区域在至少一个第一深度中具有与阴极基极区域相同的标称掺杂密度，第一深度被给定为与阴极金属化相对的阴极区域侧的垂直距离。 栅极基极区域具有比阴极基极区域更高的掺杂密度和/或栅极基极区域具有比阴极基极区域更大的深度，以便调制阻塞状态下的场并且当被驱动进入时将其从阴极散焦 动态雪崩

公开(公告)号：US08395244B2

公开(公告)日：2013-03-12

申请号：US12942410

申请日：2010-11-09

Applicant: Jan Vobecky ,  Kati Hemmann ,  Hamit Duran ,  Munaf Rahimo

Inventor： Jan Vobecky ,  Kati Hemmann ,  Hamit Duran ,  Munaf Rahimo

IPC: H01L21/02

CPC classification number: H01L29/8611 ,  H01L29/0661 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66128

Abstract: A fast recovery diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. A p-doped anode layer is arranged on the anode side. The anode layer has a doping profile and includes at least two sublayers. A first one of the sublayers has a first maximum doping concentration, which is between 2*1016 cm−3 and 2*1017 cm−3 and which is higher than the maximum doping concentration of any other sublayer. A last one of the sublayers has a last sublayer depth, which is larger than any other sublayer depth. The last sublayer depth is between 90 to 120 μm. The doping profile of the anode layer declines such that a doping concentration in a range of 5*1014 cm−3 and 1*1015 cm−3 is reached between a first depth, which is at least 20 μm, and a second depth, which is at maximum 50 μm. Such a profile of the doping concentration is achieved by using aluminum diffused layers as the at least two sublayers.

Abstract translation: 快速恢复二极管包括具有阴极侧和与阴极侧相对的阳极侧的n掺杂基极层。 p型掺杂阳极层设置在阳极侧。 阳极层具有掺杂分布并且包括至少两个子层。 第一个子层具有第一最大掺杂浓度，其在2×1016cm-3和2×1017cm-3之间，并且高于任何其它子层的最大掺杂浓度。 最后一个子层具有比任何其他子层深度大的最后一个子层深度。 最后的子层深度为90〜120μm。 阳极层的掺杂分布下降，使得在第一深度（至少20μm）和第二深度之间达到在5×10 14 cm -3和1×10 15 cm -3范围内的掺杂浓度，其中 最大为50μm。 通过使用铝扩散层作为至少两个子层来实现掺杂浓度的这种分布。

公开(公告)号：US07816706B2

公开(公告)日：2010-10-19

申请号：US12007890

申请日：2008-01-16

Applicant: Munaf Rahimo ,  Peter Streit

Inventor： Munaf Rahimo ,  Peter Streit

IPC: H01L29/745 ,  H01L21/332

CPC classification number: H01L29/102 ,  H01L29/744

Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.

Abstract translation: 具有四层npnp结构的功率半导体器件可以通过栅电极截止。 第一基极层包括与阴极区域相邻的阴极基极区域和与栅极电极相邻但与阴极区域相距一定距离的栅极基极区域。 栅极基极区域在至少一个第一深度中具有与阴极基极区域相同的标称掺杂密度，第一深度被给定为与阴极金属化相对的阴极区域侧的垂直距离。 栅极基极区域具有比阴极基极区域更高的掺杂密度和/或栅极基极区域具有比阴极基极区域更大的深度，以便调制阻塞状态下的场并且当被驱动进入时将其从阴极散焦 动态雪崩

公开(公告)号：US20100248462A1

公开(公告)日：2010-09-30

申请号：US12731977

申请日：2010-03-25

Applicant: Jan VOBECKY ,  Munaf Rahimo

Inventor： Jan VOBECKY ,  Munaf Rahimo

IPC: H01L21/22

CPC classification number: H01L21/221 ,  H01L21/26506 ,  H01L21/266

Abstract: An exemplary method is disclosed for manufacturing a power semiconductor device which has a first electrical contact on a first main side and a second electrical contact on a second main side opposite the first main side and at least a two-layer structure with layers of different conductivity types, and includes providing an n-doped wafer and creating a surface layer of palladium particles on the first main side. The wafer is irradiated on the first main side with ions. Afterwards, the palladium particles are diffused into the wafer at a temperature of not more than 750° C., by which diffusion a first p-doped layer is created. Then, the first and second electrical contacts are created. At least the irradiation with ions is performed through a mask.

Abstract translation: 公开了一种用于制造功率半导体器件的示例性方法，该功率半导体器件在第一主侧具有第一电接触，而在与第一主侧相对的第二主侧上具有第二电接触，以及至少具有不同导电层的两层结构 类型，并且包括提供n掺杂晶片并在第一主侧上产生钯颗粒的表面层。 用离子将晶片照射在第一主面上。 之后，钯粒子在不超过750℃的温度下扩散到晶片中，由此产生第一p掺杂层的扩散。 然后，产生第一和第二电触点。 至少通过掩模进行离子照射。

公开(公告)号：US20100151650A1

公开(公告)日：2010-06-17

申请号：US12635975

申请日：2009-12-11

Applicant: Arnost Kopta ,  Munaf Rahimo

Inventor： Arnost Kopta ,  Munaf Rahimo

IPC: H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395

Abstract: A method of manufacturing a power semiconductor device is provided. A first oxide layer is produced on a first main side of a substrate of a first conductivity type. A structured gate electrode layer with at least one opening is then formed on the first main side on top of the first oxide layer. A first dopant of the first conductivity type is implanted into the substrate on the first main side using the structured gate electrode layer as a mask, and the first dopant is diffused into the substrate. A second dopant of a second conductivity type is then implanted into the substrate on the first main side, and the second dopant is diffused into the substrate. After diffusing the first dopant into the substrate and before implanting the second dopant into the substrate, the first oxide layer is partially removed. The structured gate electrode layer can be used as a mask for implanting the second dopant.

Abstract translation: 提供一种制造功率半导体器件的方法。 在第一导电类型的基板的第一主侧上产生第一氧化物层。 然后在第一氧化物层的顶部的第一主侧上形成具有至少一个开口的结构化的栅极电极层。 使用结构化栅极电极层作为掩模，将第一导电类型的第一掺杂剂注入到第一主侧的衬底中，并且第一掺杂剂扩散到衬底中。 然后将第二导电类型的第二掺杂剂注入到第一主侧上的衬底中，并且将第二掺杂剂扩散到衬底中。 在将第一掺杂剂扩散到衬底中并且在将第二掺杂剂注入衬底之前，部分地去除第一氧化物层。 结构化栅极电极层可以用作用于注入第二掺杂剂的掩模。