公开(公告)号：US06229335B1

公开(公告)日：2001-05-08

申请号：US09417983

申请日：1999-10-13

申请人： Jincheng Huang ,  Nai-Shung Chang ,  Yuangtsang Liaw

发明人： Jincheng Huang ,  Nai-Shung Chang ,  Yuangtsang Liaw

IPC分类号： H03K1716

CPC分类号： H03K19/018585

摘要： An input/output buffer capable of supporting multiple transmission logic bus specifications. The input/output buffer has a coordinating controller, a logic control circuit, a first transistor, a second transistor, a first resistor element, and a second resistor element. The logic control circuit picks up a microprocessor-type signal to determine the type of microprocessors used. According to the microprocessor type, conductivity of the first transistor, the second transistor, the first resistor element and the second resistor element are reassigned to fit the particular logic bus specification of the microprocessor. Hence, a single chipset on a main circuit board is able to accommodate various types of microprocessors.

摘要翻译： 能够支持多种传输逻辑总线规格的输入/输出缓冲器。 输入/输出缓冲器具有协调控制器，逻辑控制电路，第一晶体管，第二晶体管，第一电阻元件和第二电阻元件。 逻辑控制电路拾取微处理器型信号以确定所使用的微处理器的类型。 根据微处理器类型，第一晶体管，第二晶体管，第一电阻元件和第二电阻元件的电导率被重新分配以适应微处理器的特定逻辑总线规范。 因此，主电路板上的单个芯片组能够适应各种类型的微处理器。

公开(公告)号：US06173365B2

公开(公告)日：2001-01-09

申请号：US09122454

申请日：1998-07-24

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F1200

CPC分类号： G06F12/0802

摘要： A high-performance and cost-effective cache memory system is provided for use in conjunction with a high-speed computer system. The cache memory system is used on a computer system having a central processing unit (CPU) of the type having a back-off function that can be activated to temporarily halt the CPU when receiving a back-off signal. The cache memory system is capable of enabling the back-off signal in the event that the data read request signal from the CPU is determined to be a miss. During the back-off duration of the CPU, the requested data are moved from the primary memory unit to the cache memory module. This feature allows the overall performance of the computer system to be high even though a low-speed tag random-access memory (RAM) is used in the cache memory system, allowing the computer system to be highly cost-effective to use with high performance.

摘要翻译： 提供了与高速计算机系统结合使用的高性能和具有成本效益的高速缓冲存储器系统。 高速缓冲存储器系统用于具有这种类型的中央处理单元（CPU）的计算机系统，该中央处理单元（CPU）具有可被激活以在接收到退避信号时临时停止CPU的退避功能。 高速缓冲存储器系统能够在来自CPU的数据读取请求信号被确定为错过的情况下启用退避信号。 在CPU的退避时间期间，请求的数据从主存储器单元移动到高速缓冲存储器模块。 即使在高速缓冲存储器系统中使用低速标签随机存取存储器（RAM），该功能也使得计算机系统的整体性能仍然很高，从而使计算机系统具有高性价比的高性能 。

公开(公告)号：US6148398A

公开(公告)日：2000-11-14

申请号：US286230

申请日：1999-04-05

申请人： Wen-Ching Chang ,  Lin-Hung Chang ,  Nai-Shung Chang

发明人： Wen-Ching Chang ,  Lin-Hung Chang ,  Nai-Shung Chang

IPC分类号： G06F1/22 ,  G06F9/00

CPC分类号： G06F1/22

摘要： A setting/driving circuit is provided for use in conjunction with an IC logic unit, such as a CPU having one or more multi-function pins, to provide two or more sets of data, such as a set of parameter data and a set of control data, via the same multi-function pins to the CPU. The setting/driving circuit includes a tri-state buffer and a parameter setting unit composed of two resistors and a switch, such as a jumper. When the tri-state buffer is disabled, the parameter data set by the switch is transferred to the multi-function pin of the CPU. On the other hand, when the tri-state buffer is enabled, the input data to the input port of the tri-state buffer is transferred to the multi-function pin of the CPU. The tri-state buffer can be integrated within the chip set without having to increase the total number of pins on the chip set so that the layout complexity on the motherboard can be simpler and thus easier to assemble compared to the prior art. Therefore, the proposed setting/driving circuit is easier and more cost-effective to implement on a computer motherboard than the prior art.

摘要翻译： 提供了一种设置/驱动电路，用于与诸如具有一个或多个多功能引脚的CPU的IC逻辑单元一起使用，以提供两组或更多组数据，例如一组参数数据和一组 控制数据，通过相同的多功能引脚到CPU。 设置/驱动电路包括三态缓冲器和由两个电阻器组成的参数设置单元和诸如跳线的开关。 当三态缓冲器被禁用时，由开关设置的参数数据被传送到CPU的多功能引脚。 另一方面，当启用三态缓冲器时，三态缓冲器的输入端口的输入数据被传送到CPU的多功能引脚。 三态缓冲器可以集成在芯片组中，而不必增加芯片组上的引脚总数，使得与现有技术相比，主板上的布局复杂度可以更简单并且因此更容易组装。 因此，在现有技术中，所提出的设置/驱动电路在计算机主板上的实现更容易，更具成本效益。

公开(公告)号：US07783905B2

公开(公告)日：2010-08-24

申请号：US11423722

申请日：2006-06-13

申请人： Nai-Shung Chang ,  Chia-Hsing Yu

发明人： Nai-Shung Chang ,  Chia-Hsing Yu

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3225 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.

摘要翻译： 提供了一种降低处于工作状态的计算机系统的功耗的方法。 计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。 该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电 通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。 当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

公开(公告)号：US07047430B2

公开(公告)日：2006-05-16

申请号：US09948850

申请日：2001-09-07

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F1/26

CPC分类号： G06F1/3243 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

摘要： A method of operating a chipset for saving power consumption is provided. Basic operating units, control units and input/output ports are used to simulate the operation inside the chipset. Any idling operating units are temporarily shut down, only to be activated again on demand. Ultimately, less power consumption is used and less heat is generated by the chipset.

公开(公告)号：US07024496B2

公开(公告)日：2006-04-04

申请号：US10930117

申请日：2004-08-30

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F3/00 ,  G06F13/00 ,  H03K19/003 ,  H03K17/16

CPC分类号： G06F13/4072

摘要： An I/O pad has a data transmitting circuit, a data monitoring control circuit, and a control selection circuit. The control selection circuit controls the data transmitting circuit. When it is enabled, data in the data transmitting circuit are exported to a receiving circuit. When it is disabled, data exportation stops. The data monitoring circuit receives signals of the data transmission circuit and export signals to the control selection circuit. The data monitoring circuit judges whether the data transmission is under a stable condition. If it is not, an unstable signal is exported to a first input end of the control selection circuit. A second input end of the control selection circuit receives an output enabling signal. When the data transmission is stable and the output enabling signal indicates a disable status, the control selection circuit disables the data transmitting circuit. Otherwise, the control selection circuit enables the data transmitting circuit.

摘要翻译： I / O焊盘具有数据发送电路，数据监视控制电路和控制选择电路。 控制选择电路控制数据发送电路。 当使能时，数据发送电路中的数据被输出到接收电路。 禁用数据后，数据导出停止。 数据监视电路接收数据传输电路的信号并将信号输出到控制选择电路。 数据监视电路判断数据传输是否处于稳定状态。 如果不是，则将不稳定的信号输出到控制选择电路的第一输入端。 控制选择电路的第二输入端接收输出使能信号。 当数据传输稳定并且输出使能信号指示禁止状态时，控制选择电路禁止数据发送电路。 否则，控制选择电路使能数据发送电路。

公开(公告)号：US06985987B2

公开(公告)日：2006-01-10

申请号：US10036168

申请日：2001-10-22

申请人： Nai-Shung Chang ,  Chia-Hsing Yu

发明人： Nai-Shung Chang ,  Chia-Hsing Yu

IPC分类号： G06F13/00

CPC分类号： G06F13/4068

摘要： An apparatus and a method for supporting multi-processors and a motherboard using the same are provided. The apparatus receives the pins Z36 and AK36 of the Socket-370 central processing unit to determine which type the Socket-370 central processing unit is. According to the suspend status input signal transmitted from the south bridge of the motherboard, the determined result is latched, and some appropriate circuits are coupled to the Socket-370 central processing unit via a switch circuit. Meanwhile, the suspend status input signal is delayed and used to cut off the connection between the Socket-370 central processing unit and the apparatus. The delayed suspend status input signal is further delayed and then sent to an ATX power supply to activate the whole system.

摘要翻译： 提供了一种用于支持多处理器的装置和方法以及使用该处理器的母板。 该装置接收Socket-370中央处理单元的引脚Z 36和AK 36以确定Socket-370中央处理单元的类型。 根据从主板的南桥传输的暂停状态输入信号，确定结果被锁存，并且一些适当的电路经由开关电路耦合到Socket-370中央处理单元。 同时，暂停状态输入信号被延迟并用于切断Socket-370中央处理单元与设备之间的连接。 延迟暂停状态输入信号进一步延迟，然后发送到ATX电源以激活整个系统。

公开(公告)号：US06928540B2

公开(公告)日：2005-08-09

申请号：US09974559

申请日：2001-10-09

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F1/04 ,  G06F1/08 ,  G06F1/12 ,  G06F9/00

CPC分类号： G06F1/08

摘要： A system and a method capable of automatically reading out the multiple value of clock frequency on system bus are provided. The system includes a central processing unit and a chipset. The central processing unit has a storage unit for holding a multiple value of clock frequency. The storage unit is capable of synchronizing with an external device through a serial initialization packet (SIP) protocol. The chipset attempts to synchronize with the central processing unit in a SIP protocol that uses a preset multiple value of clock frequency as a parameter. If synchronization between the central processing unit and the chipset cannot be established, the preset multiple value of clock frequency is changed and the SIP protocol is executed again. The multiple value of clock frequency is reset until synchronization is established. After synchronization, the multiple value of clock frequency in the central processing unit is retrieved and compared with the preset multiple value of clock frequency. If the retrieved multiple value of clock frequency is different from the preset value in the chipset, the preset value is replaced by the retrieved value.

摘要翻译： 提供了能够在系统总线上自动读出时钟频率的多个值的系统和方法。 该系统包括中央处理单元和芯片组。 中央处理单元具有用于保持多个时钟频率值的存储单元。 存储单元能够通过串行初始化分组（SIP）协议与外部设备同步。 芯片组尝试以SIP协议与中央处理单元同步，SIP协议使用预设的多个时钟频率值作为参数。 如果中央处理单元与芯片组之间的同步不能建立，则改变预设的时钟频率倍数，再次执行SIP协议。 复位时钟频率的多个值，直到建立同步。 同步后，检索中央处理单元中的时钟频率的多个值，并将其与预设的时钟频率倍数进行比较。 如果检索到的时钟频率的多个值与芯片组中的预设值不同，则将预置值替换为检索到的值。

公开(公告)号：US06877102B2

公开(公告)日：2005-04-05

申请号：US10013983

申请日：2001-12-10

申请人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC分类号： G06F13/40 ,  G06F1/04

CPC分类号： G06F13/4068

摘要： A chipset to support multiple CPU's and a layout method thereof. Those independent signal lines for delivering high frequency clock signals of the chipset are isolated from using by other signals without being multiplexed. Trace length of the independent signal line is shorter than that of the others. The spaces between the independent signal line and others are also larger than that between other signal lines. Signal transmission quality is significantly upgraded because the high frequency clock signal is not multiplexed and isolated from others.

摘要翻译： 支持多CPU的芯片组及其布局方法。 用于传送芯片组的高频时钟信号的这些独立信号线与其他信号的使用隔离而不被复用。 独立信号线的跟踪长度短于其他信号线。 独立信号线与其他信号线之间的空间也大于其他信号线之间的间隔。 信号传输质量显着升高，因为高频时钟信号不被复用并与其隔离。

公开(公告)号：US20050039083A1

公开(公告)日：2005-02-17

申请号：US10954509

申请日：2004-09-29

申请人： Hsiang-Chou Huang ,  Jiin Lai ,  Nai-Shung Chang

发明人： Hsiang-Chou Huang ,  Jiin Lai ,  Nai-Shung Chang

IPC分类号： G06F7/58 ,  G06F11/00 ,  G06F11/26 ,  G06F11/263

CPC分类号： G06F11/261 ,  G06F11/263

摘要： An integrated testing method is proposed to perform a test procedure on a number of computer components, concurrently, in a multitasking manner through software simulation. In this method, an initialization procedure is first performed to specify the total number of simulated operations, the FIFO buffer size, the command sequence, and the start time of operation. It is a characteristic feature of this integrated testing method that the test procedure is performed concurrently in a multitasking manner on all the components under test to operate in response to each command from the command sequence. In the event that two or more of the components under test are competing for the same resource, an arbiter is activated to perform arbitration for these competing components.

摘要翻译： 提出了一种综合测试方法，通过软件仿真以多任务方式同时对多个计算机组件执行测试程序。 在该方法中，首先执行初始化过程以指定模拟操作的总数，FIFO缓冲器大小，命令序列和操作的开始时间。 这种集成测试方法的一个特征是测试程序以多任务方式并行执行所有被测组件，以响应命令序列中的每个命令进行操作。 在被测试的两个或更多个组件竞争相同资源的情况下，仲裁器被激活以对这些竞争组件执行仲裁。