公开(公告)号：US5600569A

公开(公告)日：1997-02-04

申请号：US300802

申请日：1994-09-02

申请人： Tamotsu Nishiyama ,  Shintaro Tsubata

发明人： Tamotsu Nishiyama ,  Shintaro Tsubata

IPC分类号： G06F7/533 ,  G06F7/48 ,  G06F7/508 ,  G06F7/52 ,  G06F17/50

CPC分类号： G06F7/53 ,  G06F17/5045 ,  G06F7/52 ,  G06F7/533 ,  G06F7/4824

摘要： With respect to each bit of a multiplier factor, it is judged whether or not the multiplier factor is a variable or a constant. If the multiplier factor is a constant, it is judged whether or not a bit of concern in the multiplier factor has the value of 1. Only if the bit of concern in the multiplier factor is 1, there is generated a circuit for outputting, as a partial product, a signal indicating a multiplicand. The signal indicating the multiplicand is then shifted by one bit so that the resulting signal is newly set as the signal indicating the multiplicand. By repeatedly executing the foregoing process with respect to all the bits of the multiplier factor, a circuit for calculating a partial product with respect to each bit of the multiplier factor is generated.

摘要翻译： 关于乘数的每一位，判断乘数是否为变量或常数。 如果乘数是常数，则判断乘数中的一点关注值是否为1.只有当倍增系数中所涉及的位为1时，才产生输出电路，如 部分乘积，指示被乘数的信号。 然后，指示被乘数的信号被移位一位，使得结果信号被新设置为指示被乘数的信号。 通过对乘法器系数的所有比特重复执行上述处理，生成用于计算相对于乘数因子的每个比特的部分乘积的电路。

公开(公告)号：US4935892A

公开(公告)日：1990-06-19

申请号：US136365

申请日：1987-12-22

申请人： Tamotsu Nishiyama ,  Shigeo Kuninobu

发明人： Tamotsu Nishiyama ,  Shigeo Kuninobu

IPC分类号： G06F7/537 ,  G06F7/48 ,  G06F7/49 ,  G06F7/535

CPC分类号： G06F7/4824 ,  G06F7/5375

摘要： A high speed divider circuit which implements a shift/subtract division method utilizing signed-digital binary expressions for the internal operands includes a quotient determining circuit which determines the quotient digit from the partial remainder, and a pluarlity of arithmetic cells which determine successive quotient digits by subtracting the product of the divisor and the sequential digits from the sequential partial remainders. The arithmetic cells which process the two lowest significant digits, the cells which process the most significant digits, the cells which process the intermediate digits and the cells which determine the initial partial remainder are each specifically tailored to perform their respective functions and thereby result in a divider which requires fewer circuit elements, and is simpler to implement in an integrated circuit.

摘要翻译： 实现使用用于内部操作数的带符号数字二进制表达式的移位/减法分割方法的高速分频器电路包括：商确定电路，其从部分余数确定商数，以及通过以下方式确定连续商数的多项式： 从顺序部分余数中减去除数的乘积和顺序数字。 处理两个最低有效位的算术单元，处理最高有效位的单元，处理中间位的单元和确定初始部分余数的单元被分别专门用于执行其各自的功能，从而导致 除法器，其要求较少的电路元件，并且是简单的在集成电路中实现。

公开(公告)号：US4873660A

公开(公告)日：1989-10-10

申请号：US66817

申请日：1987-06-25

申请人： Tamotsu Nishiyama ,  Shigeo Kuninobu

发明人： Tamotsu Nishiyama ,  Shigeo Kuninobu

IPC分类号： G06F7/48 ,  G06F7/537

CPC分类号： G06F7/4824 ,  G06F7/5375

摘要： A high speed arithmetic processor which may compactly be fabricated on an LSI chip is disclosed. The arithmetic processor in a first-step arithmetic operation determines an intermediate carry (or intermediate borrow) for a higher order arithmetic operation from an internal operand such as augend (or minuend) and an addend (or subtrahend) for each digit in addition (or subtraction) of signed digit numbers, carried out as an internal arithmetic operation, and determines an intermediate sum (or intermediate difference). In a second step arithmetic operation, the processor obtains a final sum (or difference) for each digit from the intermediate sum (or intermediate difference) obtained in the first step arithmetic operation and an intermediate carry (or intermediate borrow) from a lower order arithmetic operation. The sign of an internal operand is either inverted or the internal operand is converted to 0 in accordance with the value of a control signal and then provided as the internal operand for processing in the first step arithmetic operation. Such sign inversion or conversion of the operand to zero enables the first and second step arithmetic operations to be performed utilizing addition and/or subtraction only.

摘要翻译： 公开了可以紧凑地制造在LSI芯片上的高速运算处理器。 第一步算术运算中的运算处理器从内部操作数（如加法（或minuend））和加数（或减数）中确定用于高位算术运算的中间进位（或中间借位） 作为内部算术运算进行的有符号位数的减法，并确定中间和（或中间差）。 在第二步算术运算中，处理器从第一步运算中获得的中间和（或中间差）和从低阶运算的中间进位（或中间乘法）获得每个数字的最终和（或差） 操作。 内部操作数的符号是​​反转的，或者根据控制信号的值将内部操作数转换为0，然后作为第一步算术运算中的内部操作数进行处理。 这种符号反转或操作数转换为零使得能够仅利用加法和/或减法执行第一和第二步算术运算。

公开(公告)号：US20080055058A1

公开(公告)日：2008-03-06

申请号：US11792941

申请日：2006-03-03

申请人： Tamotsu Nishiyama

发明人： Tamotsu Nishiyama

IPC分类号： B60Q11/00 ,  H04B7/00

CPC分类号： G07C5/008 ,  B60L11/1816 ,  B60L11/1824 ,  B60L11/1846 ,  B60L2240/70 ,  B60L2270/30 ,  G07C5/085 ,  H04B3/548 ,  H04B2203/547 ,  Y02T10/7005 ,  Y02T10/7072 ,  Y02T10/7291 ,  Y02T90/121 ,  Y02T90/128 ,  Y02T90/14 ,  Y02T90/16 ,  Y02T90/163 ,  Y02T90/169 ,  Y04S30/14

摘要： There are provided a communications system between a vehicle, a home and a center, a vehicle information communicating apparatus and an indoor information processing apparatus which imposes no limitation on communicating time enables bulk communication. The communications system comprises an on-board server and DSRC on-board equipment which are installed on the vehicle 10 and includes a DSRC base station 23 residing outside the vehicle which can communicate with the DSRC on-board equipment and a PC or a home server 22 residing indoors which is connected to the DSRC base station 23, the communication system having a detection means installed on the vehicle and/or an indoor detection means for detecting the state of the vehicle 10 and a communication activating means for activating the communication of information between the on-board server and the PC or the home server 22 using the detection result of either or both of the detection means.

摘要翻译： 提供了车辆，家庭和中心之间的通信系统，车辆信息通信装置和不限制通信时间的室内信息处理装置，能够进行批量通信。 通信系统包括安装在车辆10上的车载服务器和DSRC车载设备，并且包括位于车辆外部的可以与DSRC车载设备通信的DSRC基站23和PC或家庭服务器 22，其连接到DSRC基站23，具有安装在车辆上的检测装置的通信系统和/或用于检测车辆10的状态的室内检测装置和用于激活信息的通信的通信激活装置 使用检测装置中的一个或两者的检测结果，在车载服务器与PC或家庭服务器22之间。

公开(公告)号：US06789135B1

公开(公告)日：2004-09-07

申请号：US09393108

申请日：1999-09-09

申请人： Shinichi Yamamoto ,  Tamotsu Nishiyama

发明人： Shinichi Yamamoto ,  Tamotsu Nishiyama

IPC分类号： G06F1314

CPC分类号： G06F8/656

摘要： An apparatus function change service system for changing a function of an apparatus including a reconfigurable chip includes a request receiving section for receiving a request for a function change of the apparatus from a user of the apparatus; a specifying section for specifying a change to be made in the reconfigurable chip for fulfilling the request based on the request; and a changing section for performing the change in the reconfigurable chip based on the specified change to be made in the reconfigurable chip.

摘要翻译： 一种用于改变包括可重构芯片的装置的功能的装置功能改变服务系统包括：请求接收部分，用于从装置的用户接收对装置的功能改变的请求; 指定部分，用于指定在可重构芯片中进行的改变以便根据该请求来完成该请求; 以及改变部分，用于基于在可重新配置的芯片中进行的指定的改变来执行可重新配置的芯片的改变。

公开(公告)号：US5777688A

公开(公告)日：1998-07-07

申请号：US644784

申请日：1996-05-10

申请人： Jiro Miyake ,  Kazuki Ninomiya ,  Miki Urano ,  Shintaro Tsubata ,  Tamotsu Nishiyama

发明人： Jiro Miyake ,  Kazuki Ninomiya ,  Miki Urano ,  Shintaro Tsubata ,  Tamotsu Nishiyama

IPC分类号： G06F17/10 ,  H04N5/14 ,  H04N5/265 ,  H04N9/64

CPC分类号： G06F17/10 ,  H04N5/14 ,  H04N5/265

摘要： A plurality of signal processing elements are cascade-connected to form a signal processor having three signal paths. The signal processor is a small-sized device which can be shared by sum-of-products calculation and division. In each signal processing element, first and second shifters and an adder-subtracter are used for performing shift addition for multiplication of a variable by a constant which is a basis of the sum-of-products calculation. The adder-subtracter and a third shifter for shifting a result obtained by the adder-subtracter are used for performing subtraction and shifting for obtaining a partial quotient and a partial remainder of division. The partial quotient thus obtained is transferred to the signal processing element in the next stage through a flag holding circuit.

摘要翻译： 多个信号处理元件被级联连接以形成具有三个信号路径的信号处理器。 信号处理器是一个小型设备，可以通过产品总和的计算和划分来共享。 在每个信号处理元件中，第一和第二移位器和加法器减法器用于执行用于将变量乘以作为乘积和计算的基础的常数的移位加法。 加法器 - 减法器和用于移位由加减法器获得的结果的第三移位器用于执行减法和移位以获得部分商和部分余数除法。 这样获得的部分商通过标志保持电路在下一级传送到信号处理元件。

公开(公告)号：US5703800A

公开(公告)日：1997-12-30

申请号：US545204

申请日：1995-10-19

申请人： Kazuki Ninomiya ,  Keizo Sumida ,  Jiro Miyake ,  Tamotsu Nishiyama

发明人： Kazuki Ninomiya ,  Keizo Sumida ,  Jiro Miyake ,  Tamotsu Nishiyama

IPC分类号： G06F15/80 ,  G06F7/38

CPC分类号： G06F15/8046 ,  G06F15/8023

摘要： An improved signal processor is disclosed which is suitable for convergence processing of images that achieves parallel processing with a smaller bus structure. An arithmetic array is provided which is formed of ten arithmetic cells capable of concurrently operating. Each arithmetic cell is specified by a denotation of E�(column number),y(row number)! where the column number x is 1.ltoreq.x.ltoreq.4 and the row number y is x.ltoreq.y.ltoreq.4. Each arithmetic cell has a multiplier and an adder for multiply-add operation. An arithmetic cell, specified by E�x,y! where 2.ltoreq.x.ltoreq.4 and x.ltoreq.y.ltoreq.4, receives data from an E�x-1,y! arithmetic cell via a direct bus as well as from an E�x-1,y-1! arithmetic cell via an oblique bus. For example, when pixel data items as to four pixels horizontally arranged in an image are fed to the four arithmetic cells in the first column, the arithmetic cell in the fourth column provides a 4-tap horizontal filter operation result.

摘要翻译： 公开了一种改进的信号处理器，其适用于以较小的总线结构实现并行处理的图像的收敛处理。 提供由能够同时操作的十个算术单元形成的运算阵列。 每个算术单元由列号x为1 的E [（列号），y（行号）]的表示来指定， = 4。 每个算术单元具有用于乘法运算的乘法器和加法器。 由E [x，y]指定的算术单元，其中2

公开(公告)号：US5555197A

公开(公告)日：1996-09-10

申请号：US226663

申请日：1994-04-11

申请人： Kazuki Ninomiya ,  Tamotsu Nishiyama ,  Jiro Miyake ,  Katsuya Hasegawa

发明人： Kazuki Ninomiya ,  Tamotsu Nishiyama ,  Jiro Miyake ,  Katsuya Hasegawa

IPC分类号： H04N5/46 ,  H04N5/907 ,  H04N7/015 ,  H04N9/64 ,  H04N5/14

CPC分类号： H04N9/642 ,  H04N5/46 ,  H04N7/0152 ,  H04N5/907

摘要： A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

摘要翻译： 协处理器被并入包括CPU，指令高速缓存，数据存储器，总线控制器，中断控制部分和DMA控制器的处理器中。 该协处理器具有并行产品总和运算部分，比较器，I / O寄存器部分和产品总和因子寄存器部分。 在输入侧提供的帧存储器存储每像素数字化的MUSE或NTSC信号。 DMA控制输入侧帧存储器和数据存储器之间的数据传送以及在输出侧提供的帧存储器与数据存储器之间的数据传送。 存储在数据存储器中的像素数据根据广播系统通过基于软件的乘积因子的切换进行处理。

公开(公告)号：US5550714A

公开(公告)日：1996-08-27

申请号：US403452

申请日：1989-09-06

申请人： Tamotsu Nishiyama

发明人： Tamotsu Nishiyama

IPC分类号： G06F17/50

CPC分类号： G06F17/509 ,  G06F2217/74

摘要： Disclosed is here units or processing steps respectively for detecting loops in a logic circuit to determine logic levels associated with first coordinates of respective elements such that a location where the overlapping of the loops develop the maximum value is assigned as a feedback routing, for determining positional relationships between elements at the reference level to relieve congestion of routings in the vicinity of the reference level, for sequentially achieving the maximum matching on a bipartite graph constituted with connective relationships of the elements for each level beginning from the reference level to determine positional relationships related to second coordinates so as to assign elements associated with each other to the same position, and for defining virtual routing length to achieve routing in accordance with a result of sorting by use of the virtual routing lengths.

摘要翻译： 这里分别公开了用于检测逻辑电路中的环路以确定与相应元件的第一坐标相关联的逻辑电平的单元或处理步骤，使得将环路重叠的最大值的位置分配为反馈路由，以确定位置 在参考级别的元件之间的关系以减轻参考水平附近的路线的拥塞，以便在由参考水平开始的每个级别的元素的连接关系构成的二分图上顺序地实现最大匹配，以确定相关的位置关系 到第二坐标，以便将彼此相关联的元素分配到相同位置，并且用于根据通过使用虚拟路由长度进行排序的结果来定义虚拟路由长度以实现路由。

公开(公告)号：US5416721A

公开(公告)日：1995-05-16

申请号：US819227

申请日：1992-01-13

申请人： Tamotsu Nishiyama ,  Kazushi Ikeda ,  Tomoko Matsunaga

发明人： Tamotsu Nishiyama ,  Kazushi Ikeda ,  Tomoko Matsunaga

IPC分类号： G06F17/50 ,  G06F15/60

CPC分类号： G06F17/509 ,  G06F2217/74

摘要： In network charts such as logic circuit diagrams, the present invention makes it possible to perform level assignment of nodes efficiently and universally. A method for assigning levels to nodes according to the present invention includes a first step of dividing a network chart or a logic circuit into strongly connected components, a second step of providing all arcs with weights for every node of the above described strongly connected components having at least two nodes so that the inflow of arc weight may become equivalent to the outflow thereof, a third step of detecting an arc for which the weight in the above described strongly connected component becomes the maximum, and a fourth step of determining a disconnection point of a loop out of arcs for which the above described weights become the maximum or becomes its proportionate magnitude. All loops included in the network chart are thus removed.

摘要翻译： 在诸如逻辑电路图的网络图中，本发明使得可以有效地和普遍地执行节点的级别分配。 根据本发明的用于向节点分配电平的方法包括将网络图或逻辑电路划分为强连接的组件的第一步骤;向所有弧提供具有上述强连接组件的每个节点的权重的第二步骤， 至少两个节点，使得电弧重量的流入可能变得等于其流出;第三步骤，检测上述强连接部件中的重量变为最大的电弧，以及确定断开点的第四步骤 由上述权重成为最大值或成为其比例大小的弧的回路。 因此，网络图中包含的所有循环都被删除。