公开(公告)号：US20210247824A1

公开(公告)日：2021-08-12

申请号：US17240475

申请日：2021-04-26

Applicant: Oracle International Corporation

Inventor： Yifan YangGong ,  Sebastian Turullols

IPC: G06F1/20 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3234

Abstract: A power management controller is disclosed. Broadly speaking, the controller may, in response to receiving a timing signal, monitor a temperature of an integrated circuit including multiple processor clusters. The controller may generate a comparison of the temperature and a threshold value, and in response to a determination that the comparison indicates that the temperature is less than the threshold value, transition a particular processor cluster to a new power state.

公开(公告)号：US10990145B2

公开(公告)日：2021-04-27

申请号：US16525528

申请日：2019-07-29

Applicant: Oracle International Corporation

Inventor： Yifan YangGong ,  Sebastian Turullols

IPC: G06F1/32 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3234

Abstract: A power management controller is disclosed. Broadly speaking, the controller may, in response to receiving a timing signal, monitor a temperature of an integrated circuit including multiple processor clusters. The controller may generate a comparison of the temperature and a threshold value, and in response to a determination that the comparison indicates that the temperature is less than the threshold value, transition a particular processor cluster to a new power state.

公开(公告)号：US20190354150A1

公开(公告)日：2019-11-21

申请号：US16525528

申请日：2019-07-29

Applicant: Oracle International Corporation

Inventor： Yifan YangGong ,  Sebastian Turullols

IPC: G06F1/20 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/324

Abstract: A power management controller is disclosed. Broadly speaking, the controller may, in response to receiving a timing signal, monitor a temperature of an integrated circuit including multiple processor clusters. The controller may generate a comparison of the temperature and a threshold value, and in response to a determination that the comparison indicates that the temperature is less than the threshold value, transition a particular processor cluster to a new power state.

公开(公告)号：US10337932B2

公开(公告)日：2019-07-02

申请号：US14865149

申请日：2015-09-25

Applicant: Oracle International Corporation

Inventor： Venkatram Krishnaswamy ,  Sebastian Turullols

IPC: G01K15/00

Abstract: A system is disclosed, including an interface to a DUT and a testing apparatus. The DUT includes a first plurality of temperature sensing circuits. The testing apparatus may store a plurality of control values. Each control value may depend on at least two calibration values of corresponding temperature sensing circuits of a second plurality of temperature sensing circuits. The testing apparatus may generate a plurality of calibration values for the DUT. Each calibration value corresponds to one of the first plurality of temperature sensing circuits. The testing apparatus may determine a plurality of test values for the DUT. The testing apparatus may calculate a probability value, and repeat generation of the plurality of calibration values upon determining that the probability value is less than a predetermined threshold value. The probability value corresponds to a likelihood that the plurality of calibration values is accurate.

公开(公告)号：US20190011971A1

公开(公告)日：2019-01-10

申请号：US15645528

申请日：2017-07-10

Applicant: Oracle International Corporation

Inventor： Yifan YangGong ,  Sebastian Turullols

IPC: G06F1/32

Abstract: A power management controller is disclosed. Broadly speaking, the controller may, in response to detecting a timing signal, determine a total power consumption for a plurality of processor clusters, each of which includes a plurality of processor cores. The controller may determine a performance metric using the total power consumption and compare the performance metric to a limit. Based on a result of the comparison, the controller may select a new power state for at least one of the processor clusters.

公开(公告)号：US10120000B2

公开(公告)日：2018-11-06

申请号：US14799664

申请日：2015-07-15

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Sebastian Turullols

IPC: G06F1/00 ,  G01R19/25 ,  G01R19/00 ,  G05F1/10 ,  H03H7/01

Abstract: Systems, methods, and other embodiments are disclosed that are configured to provide on-chip current sensing by employing a power distribution network voltage de-convolution technique. A voltage signal on a voltage plane of a system-on-chip device is measured during operation of the system-on-chip device. The voltage signal derives from a power distribution network. The voltage signal is de-convolved, based at least in part on inverse convolution coefficients derived from the power distribution network, to recover a current signal being drawn by the system-on-chip device from the power distribution network.

公开(公告)号：US09710042B2

公开(公告)日：2017-07-18

申请号：US14461042

申请日：2014-08-15

Applicant: Oracle International Corporation

Inventor： Haowei Zhang ,  Xiaoying Shen ,  Sebastian Turullols ,  Robert T. Golla

IPC: G06F1/30 ,  G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3206 ,  G06F1/3287 ,  G06F9/3869 ,  Y02D10/171

Abstract: Embodiments of the invention provide adaptive power ramp control (APRC) in microprocessors. One implementation of the APRC can compute a present core power and a present power ramp condition in the microprocessor, for example, to determine whether the present power is in a particular predefined control zone and whether the present power ramp is greater than a predefined threshold for that control zone. Those determinations can indicate a likelihood of an imminent, undesirable power ramp condition and can inform entry into a control mode. The APRC can generate an appropriate stall control signal in response to its present control mode, and the stall control signal can stall operation of at least one functional unit of the microprocessor according to a predefined stall pattern. This can effectively combat the imminent power ramp condition by reducing the power usage of the microprocessor.

公开(公告)号：US09507405B2

公开(公告)日：2016-11-29

申请号：US14308079

申请日：2014-06-18

Applicant: Oracle International Corporation

Inventor： Venkatram Krishnaswamy ,  Georgios K Konstadinidis ,  Sebastian Turullols ,  Yifan YangGong

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3243 ,  Y02D10/126 ,  Y02D10/152

Abstract: A system includes a power management unit that may monitor the power consumed by a processor including a plurality of processor core. The power management unit may throttle or reduce the operating frequency of the processor cores by applying a number of throttle events in response to determining that the plurality of cores is operating above a predetermined power threshold during a given monitoring cycle. The number of throttle events may be based upon a relative priority of each of the plurality of processor cores to one another and an amount that the processor is operating above the predetermined power threshold. The number of throttle events may correspond to a portion of a total number of throttle events, and which may be dynamically determined during operation based upon a proportionality constant and the difference between the total power consumed by the processor and a predetermined power threshold.

Abstract translation: 一种系统包括能够监视包括多个处理器核心的处理器消耗的功率的电力管理单元。 电源管理单元可以通过施加多个节气门事件来响应于在给定的监视循环期间确定多个核在高于预定功率阈值的情况下运行，来节流或降低处理器核心的工作频率。 油门事件的数量可以基于多个处理器核心中的每一个相对于彼此的相对优先级，以及处理器在高于预定功率阈值的情况下操作的量。 节气门事件的数量可以对应于节气门事件总数的一部分，并且其可以在操作期间基于比例常数和处理器消耗的总功率与预定功率阈值之间的差异来动态地确定。

公开(公告)号：US11762444B2

公开(公告)日：2023-09-19

申请号：US17388830

申请日：2021-07-29

Applicant: Oracle International Corporation

Inventor： Lin Zhang ,  Yifan YangGong ,  Sebastian Turullols

IPC: G06F1/28 ,  G06F1/08

CPC classification number: G06F1/28 ,  G06F1/08

Abstract: A method for determining power dissipation within a computer system is disclosed. A circuit block may receive a regulated voltage level on a power supply signal generated by a voltage regulator circuit. A power control circuit may measure a current drawn by the circuit block, and determine a real-time voltage level for the power supply signal using the current and based on a slope value and a zero-load voltage level. Additionally, power control circuit may determine a power dissipation for the circuit block using the current and the real-time voltage level, and adjust an operation parameter of the circuit block based on the power dissipation.

公开(公告)号：US10656205B2

公开(公告)日：2020-05-19

申请号：US15886566

申请日：2018-02-01

Applicant: Oracle International Corporation

Inventor： Mark Semmelmeyer ,  Ali Vahidsafa ,  Sebastian Turullols ,  Scott Cooke ,  Senthilkumar Diraviam ,  Preethi Sama

IPC: G01R31/3183 ,  G01R31/28 ,  G01R31/319 ,  G01R31/317

Abstract: Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.