公开(公告)号：US20230412795A1

公开(公告)日：2023-12-21

申请号：US18242133

申请日：2023-09-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186

CPC classification number: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes memory and circuitry. The circuitry, using the memory, (i) selects a mode from among a plurality of modes each for deriving a motion vector, and derives a motion vector for a current block via the selected mode, and (ii) performs inter prediction encoding on the current block, using the derived motion vector, via one of a skip mode and a non-skip mode different from the skip mode. The plurality of modes include a plurality of first modes each for predicting the motion vector for the current block based on an encoded block neighboring the current block without encoding information indicating a motion vector into a stream. When a second mode included in the plurality of first modes is selected, the current block is encoded via the non-skip mode regardless of presence or absence of a residual coefficient.

公开(公告)号：US20230396776A1

公开(公告)日：2023-12-07

申请号：US18234504

申请日：2023-08-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Ru Ling LIAO ,  Chong Soon LIM ,  Han Boon TEO ,  Hai Wei SUN ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/159 ,  H04N19/117 ,  H04N19/182

CPC classification number: H04N19/159 ,  H04N19/117 ,  H04N19/182

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry: derives an absolute value of a sum of gradient values in first and second ranges; derives, as a first parameter, a total sum of absolute values of sums of gradient values derived respectively for pairs of relative pixel positions; derives a pixel difference value between pixel values in the first and second ranges; inverts or maintains a plus or minus sign of the pixel difference value, according to a plus or minus sign of the sum of the gradient values indicating the sum of the gradient values in the first and second ranges; derives, as a second parameter, a total sum of pixel difference values each having the plus or minus sign inverted or maintained, the pixel difference values derived respectively for the relative pixel positions; and generates a prediction image using the first and second parameters.

公开(公告)号：US20230396761A1

公开(公告)日：2023-12-07

申请号：US18451690

申请日：2023-08-17

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/117 ,  H04N19/103 ,  H04N19/176 ,  H04N19/182

CPC classification number: H04N19/117 ,  H04N19/103 ,  H04N19/176 ,  H04N19/182

Abstract: Various embodiments provide a decoder configured to select a filter based on a block size of a first block and a block size of a second block in an image, and change values of pixels in the first block and the second block. The filter includes a first set of multipliers and a first set of offsets for the first block, and a second set of multipliers and a second set of offsets for the second block. The values of the pixels in the first block and the second block are changed by performing multiplication with each multiplier in the first set of multipliers, by performing multiplication with each multiplier in the second set of multipliers, and by using the first set of offsets and the second set of offsets.

公开(公告)号：US20230379519A1

公开(公告)日：2023-11-23

申请号：US18228051

申请日：2023-07-31

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa TOMA ,  Noritaka IGUCHI ,  Takahiro NISHI ,  Hisaya KATOU

IPC: H04N21/242 ,  H04H20/93 ,  H04N21/8547 ,  H04H60/13 ,  H04N21/462 ,  H04N21/61 ,  H04N21/43

CPC classification number: H04N21/242 ,  H04H20/93 ,  H04N21/8547 ,  H04H60/13 ,  H04N21/4622 ,  H04N21/6125 ,  H04N21/6112 ,  H04N21/43072 ,  H04N21/4302 ,  H04H20/18

Abstract: A transmitting method for transmitting contents using a broadcast wave and a communication path comprises: including content information in application control information when transmitting the contents using both the broadcast wave and the communication path, the content information being information for synchronizing a content transmitted by using the broadcast wave with a content transmitted by using the communication path at a reception side that receives the contents and being related to the content transmitted by using the communication path; and transmitting the application control information by using at least the broadcast wave in the broadcast wave and the communication path. As a result, a contents transmitting method is provided for enabling a quick access to contents through communication when the contents are reproduced by a combination of broadcast and communication on the receiving side.

公开(公告)号：US20230353790A1

公开(公告)日：2023-11-02

申请号：US18052108

申请日：2022-11-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chu Tong WANG ,  Chong Soon LIM ,  Han Boon TEO ,  Hai Wei SUN ,  Jing Ya LI ,  Che-Wei KUO ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/17 ,  H04N19/186 ,  H04N19/82 ,  H04N19/117 ,  H04N19/132 ,  H04N19/167

CPC classification number: H04N19/82 ,  H04N19/117 ,  H04N19/132 ,  H04N19/167 ,  H04N19/17 ,  H04N19/186

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in response to a first reconstructed image sample being located outside a virtual boundary, duplicates a reconstructed sample located inside and adjacent to the virtual boundary to generate the first reconstructed image sample. The circuitry generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to the first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value.

公开(公告)号：US20230345000A1

公开(公告)日：2023-10-26

申请号：US18214653

申请日：2023-06-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Masato OHKAWA ,  Hideo SAITOU ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Ryuichi KANOH

IPC: H04N19/176 ,  H04N19/12 ,  H04N19/124 ,  H04N19/625

CPC classification number: H04N19/12 ,  H04N19/124 ,  H04N19/176 ,  H04N19/625

Abstract: When a transform-basis adaptive selection mode is enabled, an encoder that transforms residuals of a current block to encode an image: adaptively selects a first horizontal transform basis from among one or more transform basis candidates when a horizontal size of the current block is greater than a first horizontal threshold size; otherwise selects a fixed horizontal transform basis as a first horizontal transform basis; adaptively selects a first vertical transform basis from among the one or more transform basis candidates when a vertical size of the current block is greater than a first vertical threshold size; otherwise selects a fixed vertical transform basis as a first vertical transform basis; and generates first transform coefficients by performing a first horizontal transform and a first vertical transform on the residuals of the current block, using the first horizontal transform basis selected and the first vertical transform basis selected, respectively.

公开(公告)号：US20230300367A1

公开(公告)日：2023-09-21

申请号：US18200807

申请日：2023-05-23

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/52 ,  H04N19/176 ,  H04N19/186

CPC classification number: H04N19/52 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: stores MV information and correction processing information into a FIFO buffer for an HMVP mode in association, the MV information being derived for a processed block and correction processing information being related to correction processing of a prediction image of the processed block; registers, in a prediction candidate list for a merge mode, one or more prediction candidates each being a combination of MV information and correction processing information, the prediction candidates including a prediction candidate which is a combination of the motion vector information and the correction processing information stored in the FIFO buffer; and selects a prediction candidate from the prediction candidate list when a current block is to be processed in the merge mode, and performs correction processing of a prediction image of the current block, based on the correction processing information.

公开(公告)号：US20230206508A1

公开(公告)日：2023-06-29

申请号：US18117687

申请日：2023-03-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Toshiyasu SUGIO ,  Takahiro NISHI ,  Tadamasa TOMA ,  Toru MATSUNOBU ,  Satoshi YOSHIKAWA ,  Tatsuya KOYAMA

IPC: G06T9/00 ,  H04N13/275 ,  G06T17/05 ,  H04L67/01 ,  G01C21/00

CPC classification number: G06T9/00 ,  H04N13/275 ,  G06T17/05 ,  H04L67/01 ,  G01C21/3848 ,  G01C21/3885 ,  G01S17/89

Abstract: A three-dimensional data creation method in a client device includes: creating three-dimensional data of a surrounding area of the client device using sensor information that is obtained through a sensor equipped in the client device and indicates a surrounding condition of the client device; estimating a self-location of the client device using the three-dimensional data created; and transmitting the sensor information obtained to a server or an other client device.

公开(公告)号：US20230156188A1

公开(公告)日：2023-05-18

申请号：US18150659

申请日：2023-01-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE

IPC: H04N19/117 ,  H04N19/176 ,  H04N19/146

CPC classification number: H04N19/117 ,  H04N19/176 ,  H04N19/146

Abstract: A decoder comprises circuitry and memory. The circuitry, using the memory, in operation, determines a number of first pixels and a number of second pixels used in a deblocking filter process, wherein the first pixels are located at an upper side of a block boundary and the second pixels are located at a lower side of the block boundary, and performs the deblocking filter process on the block boundary. The number of the first pixels and the number of the second pixels are selected from among candidates, wherein the candidates include at least 4 and M larger than 4. Response to a location of the block boundary being a predetermined location, the number of the first pixels used in the deblocking filter process is limited to be 4.

公开(公告)号：US20230096489A1

公开(公告)日：2023-03-30

申请号：US17944866

申请日：2022-09-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ru Ling LIAO ,  Chong Soon LIM ,  Hai Wei SUN ,  Han Boon TEO ,  Jing Ya LI ,  Sughosh Pavan SHASHIDHAR ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes: circuitry; and memory coupled to the circuitry. The circuitry, in operation, stores a first parameter into a bitstream, the first parameter indicating, as a prediction mode, one of (i) a multiple prediction mode in which a prediction image is generated by overlapping an inter prediction image of a current block and an intra prediction image of the current block and (ii) one of a plurality of prediction modes including a non-rectangular mode in which a prediction image is generated for each non-rectangular partition in the current block, and encodes the current block according to the prediction mode.