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129 条记录 (耗时 0.038 秒)

    System and method for improving spatial resolution of electron holography
    32.
    发明授权
    System and method for improving spatial resolution of electron holography 失效

    公开(公告)号：US07102145B2

    公开(公告)日：2006-09-05

    申请号：US10972696

    申请日：2004-10-25

    申请人： Anthony G. Domenicucci ,  Yun-Yu Wang

    发明人： Anthony G. Domenicucci ,  Yun-Yu Wang

    IPC分类号： G01N23/04

    CPC分类号： H01J37/26 ,  G03H5/00 ,  H01J37/04 ,  H01J2237/0492 ,  H01J2237/1514 ,  H01J2237/2614

    摘要： A method for enhancing spatial resolution of a transmission electron microscopy TEM) system configured for electron holography. In an exemplary embodiment, the method includes configuring a first lens to form an initial virtual source with respect to an incident parallel beam, the initial virtual source positioned at a back focal plane of said first lens. A second lens is configured to form an intermediate virtual source with respect to the incident parallel beam, the position of said intermediate virtual source being dependent upon a focal length of the first lens and a focal length of the second lens. A third lens is configured to form a final virtual source with respect to the incident parallel beam, wherein the third lens has a focal length such that a front focal plane of the third lens lies beyond the position of the intermediate virtual source, with respect to a biprism location.

    REDUCING DISLOCATION FORMATION IN SEMICONDUCTOR DEVICES THROUGH TARGETED CARBON IMPLANTATION
    33.
    发明申请
    REDUCING DISLOCATION FORMATION IN SEMICONDUCTOR DEVICES THROUGH TARGETED CARBON IMPLANTATION 失效
    通过目标碳植入减少半导体器件中的分离形成

    公开(公告)号：US20120184075A1

    公开(公告)日：2012-07-19

    申请号：US13009020

    申请日：2011-01-19

    申请人： Anthony G. Domenicucci ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel C. Ontalus ,  Yun-Yu Wang

    发明人： Anthony G. Domenicucci ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel C. Ontalus ,  Yun-Yu Wang

    IPC分类号： H01L21/336 ,  H01L21/84

    CPC分类号： H01L29/7847 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.

    摘要翻译： 形成半导体器件的方法包括将非晶化物质注入晶体半导体衬底中，所述衬底具有在其上形成的晶体管栅极结构。 碳被植入到基底的非晶化区域中，其特定的植入条件被定制，使得碳类的峰值浓度与堆垛层错的结束一致，其中在重结晶退火期间产生堆垛层错。 植入的碳引脚部分位错，以防止位错从堆垛层错的末端脱离，并移动到晶体管栅极结构正下方的衬底区域。 这消除了导致设备泄漏失败的缺陷。

    PROGRAMMABLE PRECISION RESISTOR AND METHOD OF PROGRAMMING THE SAME
    34.
    发明申请
    PROGRAMMABLE PRECISION RESISTOR AND METHOD OF PROGRAMMING THE SAME 有权
    可编程精度电阻器及其编程方法

    公开(公告)号：US20100025819A1

    公开(公告)日：2010-02-04

    申请号：US12185375

    申请日：2008-08-04

    申请人： Anthony G. Domenicucci ,  Terence L. Kane ,  Michael Tenney ,  Yun-Yu Wang

    发明人： Anthony G. Domenicucci ,  Terence L. Kane ,  Michael Tenney ,  Yun-Yu Wang

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5256 ,  H01L23/5228 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of metal than the first metal semiconductor alloy. Due to the stoichiometric differences between the first and second metal semiconductor alloys, the link portion has a higher resistance after programming than prior to programming. The shift in electrical resistance well controlled, which is advantageously employed to as a programmable precision resistor.

    摘要翻译： 第一电极和第二电极之间的连接部分包括半导体连接部分和包括第一金属半导体合金的金属半导体合金连接部分。 电脉冲将整个连接部分转换成具有比第一金属半导体合金低的金属浓度的第二金属半导体合金。 由于第一和第二金属半导体合金之间的化学计量差异，链接部分在编程之后具有比编程之前更高的电阻。 良好控制的电阻的偏移，其有利地用作可编程精密电阻器。

    Method of fabricating a device using low temperature anneal processes, a device and design structure
    35.
    发明授权
    Method of fabricating a device using low temperature anneal processes, a device and design structure 有权
    使用低温退火工艺制造器件的方法，器件和设计结构

    公开(公告)号：US08490029B2

    公开(公告)日：2013-07-16

    申请号：US13421400

    申请日：2012-03-15

    申请人： Anthony G. Domenicucci ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

    发明人： Anthony G. Domenicucci ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

    IPC分类号： G06F17/50

    CPC分类号： H01L21/324 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7847

    摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

    摘要翻译： 提供了使用退火处理序列制造器件的方法。 更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。 该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。 该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。

    Reducing dislocation formation in semiconductor devices through targeted carbon implantation
    37.
    发明授权
    Reducing dislocation formation in semiconductor devices through targeted carbon implantation 失效
    通过目标碳注入减少半导体器件中的位错形成

    公开(公告)号：US08343825B2

    公开(公告)日：2013-01-01

    申请号：US13009020

    申请日：2011-01-19

    申请人： Anthony G. Domenicucci ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel C. Ontalus ,  Yun-Yu Wang

    发明人： Anthony G. Domenicucci ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel C. Ontalus ,  Yun-Yu Wang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7847 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.

    摘要翻译： 形成半导体器件的方法包括将非晶化物质注入晶体半导体衬底中，所述衬底具有在其上形成的晶体管栅极结构。 碳被植入到基底的非晶化区域中，其特定的植入条件被定制，使得碳类的峰值浓度与堆垛层错的结束一致，其中在重结晶退火期间产生堆垛层错。 植入的碳引脚部分位错，以防止位错从堆垛层错的末端脱离，并移动到晶体管栅极结构正下方的衬底区域。 这消除了导致设备泄漏失败的缺陷。

    Method of reducing stacking faults through annealing
    38.
    发明授权
    Method of reducing stacking faults through annealing 失效
    通过退火减少堆垛层错的方法

    公开(公告)号：US07956417B2

    公开(公告)日：2011-06-07

    申请号：US12839588

    申请日：2010-07-20

    申请人： Yun-Yu Wang ,  Christopher D. Sheraw ,  Anthony G. Domenicucci ,  Linda Black ,  Judson R. Holt ,  David M. Fried

    发明人： Yun-Yu Wang ,  Christopher D. Sheraw ,  Anthony G. Domenicucci ,  Linda Black ,  Judson R. Holt ,  David M. Fried

    IPC分类号： H01L27/12

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

    摘要： Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.

    摘要翻译： 因此，在本发明的一个实施例中，提供了一种用于减少外延半导体层中的堆垛层错的方法。 根据这种方法，提供了一种衬底，其包括包括第一半导体材料的第一单晶半导体区域，第一半导体区域具有<110>晶体取向。 在第一半导体区域上生长包括第一半导体材料的外延层，具有<110>晶体取向的外延层。 然后在包括氢气的环境中，在大于1100摄氏度的温度下将衬底与外延层退火，由此退火步骤减少外延层中的堆垛层错。

    Decoder for a stationary switch machine
    39.
    发明授权
    Decoder for a stationary switch machine 有权
    固定式开关机的解码器

    公开(公告)号：US07820501B2

    公开(公告)日：2010-10-26

    申请号：US11548428

    申请日：2006-10-11

    申请人： Yun-Yu Wang ,  Christopher D. Sheraw ,  Anthony G. Domenicucci ,  Linda Black ,  Judson R. Holt ,  David M. Fried

    发明人： Yun-Yu Wang ,  Christopher D. Sheraw ,  Anthony G. Domenicucci ,  Linda Black ,  Judson R. Holt ,  David M. Fried

    IPC分类号： H01L21/336

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

    摘要： Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.

    摘要翻译： 因此，在本发明的一个实施例中，提供了一种用于减少外延半导体层中的堆垛层错的方法。 根据这种方法，提供了一种衬底，其包括包括第一半导体材料的第一单晶半导体区域，第一半导体区域具有<110>晶体取向。 在第一半导体区域上生长包括第一半导体材料的外延层，具有<110>晶体取向的外延层。 然后在包括氢气的环境中，在大于1100摄氏度的温度下将衬底与外延层退火，由此退火步骤减少外延层中的堆垛层错。