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    Distributed random access memory in a programmable logic device
    33.
    发明授权
    Distributed random access memory in a programmable logic device 有权
    可编程逻辑器件中的分布式随机存取存储器

    公开(公告)号：US07084665B1

    公开(公告)日：2006-08-01

    申请号：US10897743

    申请日：2004-07-22

    申请人： David Lewis ,  Paul Leventis ,  Vaughn Betz

    发明人： David Lewis ,  Paul Leventis ,  Vaughn Betz

    IPC分类号： H03K19/177

    CPC分类号： H03K19/1776 ,  H03K19/17736

    摘要： Distributed random access memory in a programmable logic device uses configuration RAM bits as bits of the distributed RAM. A single write path is used to provide both configuration data and user write data. Selection circuitry, such as a multiplexer, is used to determine whether the single write path carries configuration data or user write data. In another aspect of the invention, the configuration RAM bits are used as to construct a shift register by adding pass transistors to chain the configuration RAM bits together, and clocking alternate pass transistors with two clocks 180° out of phase with one another.

    摘要翻译： 可编程逻辑器件中的分布式随机存取存储器使用配置RAM位作为分布式RAM的位。 单个写入路径用于提供配置数据和用户写入数据。 选择电路，例如多路复用器，用于确定单个写入路径是否携带配置数据或用户写入数据。 在本发明的另一方面，配置RAM位用于构造移位寄存器，通过添加传输晶体管将配置RAM位链连接在一起，并且以彼此相位180°异相的两个时钟计​​时交替传输晶体管。

    Simultaneous switching noise optimization
    35.
    发明授权
    Simultaneous switching noise optimization 有权
    同时开关噪声优化

    公开(公告)号：US08694946B1

    公开(公告)日：2014-04-08

    申请号：US12465452

    申请日：2009-05-13

    申请人： Joshua David Fender ,  Navid Azizi ,  Paul Leventis

    发明人： Joshua David Fender ,  Navid Azizi ,  Paul Leventis

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/504 ,  G06F2217/82

    摘要： This invention provides methods, computer program products, and systems to guide a user in optimizing the Simultaneous Switching Noise (SSN) of an electronic device by using visual approaches on a graphical user interface (GUI). Also provided is an interactive feedback mechanism that enables the user to evaluate the effectiveness of an optimization method. A matrix representation of the different I/O pins on the device shows the level of SSN at different victim pins caused by switching aggressor pins. The SSN is depicted using different graphical representations. Associated with the SSN of each victim pin is the graphical representation of its accuracy. The accuracy rating denotes the reliability of the SSN and is an indication of how sensitive a victim pin is to errors. In the interactive feedback mechanism, user input on SSN optimization is received and used to calculate the new SSN and accuracy rating of different victim pins on the device. The new data is then updated in a timely manner on the GUI.

    摘要翻译： 本发明提供了通过使用图形用户界面（GUI）上的可视方法来指导用户优化电子设备的同时切换噪声（SSN）的方法，计算机程序产品和系统。 还提供了一种交互式反馈机制，使得用户能够评估优化方法的有效性。 设备上不同I / O引脚的矩阵表示显示了由切换引脚引起的不同受扰引脚上的SSN电平。 使用不同的图形表示描绘SSN。 与每个受害者引脚的SSN相关联的是其精度的图形表示。 精度等级表示SSN的可靠性，并且表示受害者引脚对错误的敏感程度。 在交互式反馈机制中，接收SSN优化用户输入，用于计算设备上不同受害引脚的新SSN和精度等级。 然后在GUI上及时更新新数据。

    Pessimism removal in the modeling of simultaneous switching noise
    36.
    发明授权
    Pessimism removal in the modeling of simultaneous switching noise 有权
    同步开关噪声建模中的悲观消除

    公开(公告)号：US08443321B1

    公开(公告)日：2013-05-14

    申请号：US12137407

    申请日：2008-06-11

    申请人： Joshua David Fender ,  Kamal Patel ,  Navid Azizi ,  Paul Leventis

    发明人： Joshua David Fender ,  Kamal Patel ,  Navid Azizi ,  Paul Leventis

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F2217/82

    摘要： Methods for determining induced noise on a given victim by a set of aggressor signals are presented, and for identifying the worst case aggressor switching time alignment that causes the worst case victim noise. The method removes circuit analysis pessimism related to simultaneous switching noise (SSN) in a circuit design tool by determining physically impossible combinations of victim-aggressor input/output (I/O) pins in a circuit design and culling out the impossible combinations from the list of possible victim-aggressor combinations. The method further performs a switching window SSN analysis of the circuit design with a common uncertainty removal algorithm taking into consideration the list of possible victim-aggressor combinations, and determines the maximum voltage noise induced on I/O pins of the circuit design. The results of the noise analysis are displayed to the user.

    摘要翻译： 提出了通过一组侵略者信号确定给定受害者的感应噪声的方法，并且用于识别导致最坏情况的受害者噪声的最坏情况侵权者切换时间对准。 该方法通过确定电路设计中的受害者 - 侵入者输入/输出（I / O）引脚的物理不可能组合，并从列表中剔除不可能的组合，从而消除了电路设计工具中与同时开关噪声（SSN）相关的电路分析悲观情绪 可能的受害者 - 侵略者组合。 该方法还考虑到可能的受害者 - 侵略者组合的列表，执行具有公共不确定性去除算法的电路设计的切换窗口SSN分析，并且确定在电路设计的I / O引脚上引起的最大电压噪声。 噪声分析的结果显示给用户。

    Method and apparatus for enhancing signal routability
    38.
    发明授权
    Method and apparatus for enhancing signal routability 有权
    用于增强信号可路由性的方法和装置

    公开(公告)号：US07185306B1

    公开(公告)日：2007-02-27

    申请号：US10915647

    申请日：2004-08-09

    申请人： Paul Leventis ,  David Cashman

    发明人： Paul Leventis ,  David Cashman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method for enhancing signal routability within an integrated circuit is provided. The method initiates with examining an outer edge of a sequence of logical array blocks. The method includes identifying an undriven routing wire in a vicinity of the outer edge. An underutilized driver proximate to the undriven routing wire is also identified. Then, the underutilized driver is coupled to the undriven routing wire. A computer readable medium and an integrated circuit are also provided.

    摘要翻译： 提供了一种用于增强集成电路内的信号可路由性的方法。 该方法通过检查逻辑阵列块序列的外边缘来启动。 该方法包括识别外边缘附近的未驱动布线。 还识别了靠近未驱动路线的未充分利用的驾驶员。 然后，未充分利用的驱动器耦合到未驱动的布线。 还提供了计算机可读介质和集成电路。

    Routing architecture for a programmable logic device
    39.
    发明授权
    Routing architecture for a programmable logic device 失效
    可编程逻辑器件的路由架构

    公开(公告)号：US06970014B1

    公开(公告)日：2005-11-29

    申请号：US10623709

    申请日：2003-07-21

    申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

    发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736

    摘要： An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides.

    摘要翻译： 本发明的实施例涉及在可编程逻辑器件（“PLD”）内互连诸如逻辑阵列块（“LAB”）的功能块的3边路由架构。 在三面路由架构中，功能块第一侧的输入和输出连接到第一通道，功能块第二侧上的输入和输出连接到第二通道，其中第二侧与第一通道相反 侧。 功能块第三侧的输入和输出连接到第三个通道。 与功能块的第四侧相关联的与第三侧相反的第四侧的第四通道仅耦合到第一通道和第二通道。 在一种配置中，第一侧，第二侧和第三侧中的每一个上的输入和输出具有相等数量的输入和输出。 在该配置中，第一通道，第二通道和第三通道中的每一个具有相同的宽度。 在另一种构造中，第一侧，第二侧或第三侧中的一个上的引脚数目与另一侧上的引脚数不同。

    Power-driven timing analysis and placement for programmable logic
    40.
    发明授权
    Power-driven timing analysis and placement for programmable logic 有权
    用于可编程逻辑的功率驱动时序分析和放置

    公开(公告)号：US08099692B1

    公开(公告)日：2012-01-17

    申请号：US12953764

    申请日：2010-11-24

    申请人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    发明人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  Y02T10/82

    摘要： An integrated circuit is divided into two or more different regions, each region being a different voltage domain. In each of the regions, a voltage drop and its impact on performance will be quantified. A place and route engine (or another tool of a computer-aided design flow) will then take these timing considerations into account while performing partitioning of the device. A user's logic design is implemented into the logic array blocks taking into a voltage drop seen at those logic array blocks. Faster paths of the logic design are placed into faster logic array blocks, such as those in a core region of the integrated circuit.

    摘要翻译： 集成电路被分为两个或更多个不同的区域，每个区域是不同的电压域。 在每个区域，电压降及其对性能的影响将被量化。 然后，在执行设备分区时，会考虑到这些时间考虑因素，地方和路线引擎（或计算机辅助设计流程的另一个工具）将考虑这些时间考虑因素。 用户的逻辑设计被实现为在这些逻辑阵列块处看到的电压降的逻辑阵列块中。 将逻辑设计的更快的路径放置在更快的逻辑阵列块中，例如集成电路的核心区域中的那些。