利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

177 条记录 (耗时 0.027 秒)

    MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation
    31.
    发明授权
    MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation 有权
    MOS晶体管形成工艺包括用于改善硅化物形成的后间隔蚀刻表面处理

    公开(公告)号：US06171919B2

    公开(公告)日：2001-01-09

    申请号：US09361155

    申请日：1999-07-27

    申请人： Paul R. Besser ,  Minh Van Ngo ,  Simon S. Chan ,  Angela T. Hui

    发明人： Paul R. Besser ,  Minh Van Ngo ,  Simon S. Chan ,  Angela T. Hui

    IPC分类号： H01L21336

    CPC分类号： H01L29/665

    摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.

    摘要翻译： 通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣 。 实施例包括通过进行氢离子等离子体处理来除去碳质残渣。

    Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation
    32.
    发明授权
    Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation 有权
    在具有沉积硅层的半导体晶片中形成超浅结的方法，以减少在水化过程中的硅消耗

    公开(公告)号：US6165903A

    公开(公告)日：2000-12-26

    申请号：US185516

    申请日：1998-11-04

    申请人： Paul R. Besser ,  Nick Kepler ,  Karsten Wieczorek

    发明人： Paul R. Besser ,  Nick Kepler ,  Karsten Wieczorek

    IPC分类号： H01L21/285 ,  H01L21/44

    CPC分类号： H01L21/28525 ,  H01L21/28518

    摘要： A method for forming ultra shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation supplies additional silicon during the salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high resistivity metal silicide regions are formed on the gate and source/drain junctions. Silicon is then deposited in a layer on the high resistivity metal silicide regions. An annealing step is then performed to form low resistivity metal silicide regions on the gate and source/drain junctions. The deposited silicon is a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide (such as CoSi) to a low resistivity metal silicide (such as CoSi.sub.2). Since the additional silicon provided in the deposited layer is consumed, there is reduced consumption of the silicon from the ultra-shallow junctions, thereby preventing the bottom of the silicide regions from reaching the bottom of the source/drain junctions.

    摘要翻译： 用于在半衰期期间形成超浅结的方法，其中在硅化过程中硅消耗减少，在硫化过程中提供额外的硅。 在半导体器件中形成栅极和源极/漏极结之后，在栅极和源极/漏极结上形成高电阻金属硅化物区域。 然后将硅沉积在高电阻率金属硅化物区域上的层中。 然后执行退火步骤以在栅极和源极/漏极结上形成低电阻率金属硅化物区域。 沉积的硅是在将高电阻率金属硅化物（例如CoSi）转变成低电阻率金属硅化物（例如CoSi 2）期间用作扩散物质的硅源。 由于在沉积层中提供的附加硅被消耗，所以硅从超浅结的消耗减少，从而防止硅化物区的底部到达源极/漏极结的底部。

    MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE
    33.
    发明申请
    MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE 有权
    用于互连结构的多层障碍层

    公开(公告)号：US20140024212A1

    公开(公告)日：2014-01-23

    申请号：US13554020

    申请日：2012-07-20

    申请人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    发明人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76873 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

    摘要翻译： 形成互连结构的方法包括在基板的电介质层中形成凹部。 形成粘合阻挡层以使凹部成线。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 该凹部填充有填充层。

    METHOD TO REDUCE MOL DAMAGE ON NiSi
    34.
    发明申请
    METHOD TO REDUCE MOL DAMAGE ON NiSi 有权
    减少镍硅膜损伤的方法

    公开(公告)号：US20100193876A1

    公开(公告)日：2010-08-05

    申请号：US12366378

    申请日：2009-02-05

    申请人： Karthik Ramani ,  Paul R. Besser

    发明人： Karthik Ramani ,  Paul R. Besser

    IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L21/77 ,  H01L21/18

    CPC分类号： H01L21/823807 ,  H01L21/28052 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/458 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

    摘要： Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance.

    摘要翻译： 晶体管器件形成有硅化镍层，配制成防止去除上覆应力衬垫时的退化。 实施方案包括具有镍化硅层的晶体管，其铂组分梯度朝向其上表面增加铂含量，即铂在远离栅电极和源/漏区的方向上增加。 实施例包括形成具有第一量的铂的第一镍层，并在第一层镍上形成具有第二量铂的第二层镍，第二重量百分比的铂大于第一重量百分数。 然后将镍层退火以形成铂化合物梯度朝向上表面逐渐增加的铂硅化镍层。 铂浓度梯度在后续处理期间保护硅化镍层，如在蚀刻期间去除上覆的应力衬垫，从而避免器件性能的降低。

    Method and apparatus for controlling the thickness of a selective epitaxial growth layer
    38.
    发明授权
    Method and apparatus for controlling the thickness of a selective epitaxial growth layer 有权
    用于控制选择性外延生长层厚度的方法和装置

    公开(公告)号：US07402207B1

    公开(公告)日：2008-07-22

    申请号：US10839378

    申请日：2004-05-05

    申请人： Paul R. Besser ,  Eric N. Paton ,  William G. En

    发明人： Paul R. Besser ,  Eric N. Paton ,  William G. En

    IPC分类号： C30B21/04

    CPC分类号： C30B25/16 ,  G01B11/0616 ,  H01L21/67167 ,  H01L21/67207 ,  H01L21/67745 ,  Y10T117/1004 ,  Y10T117/1008

    摘要： Methods and systems for permitting thickness control of the selective epitaxial growth (SEG) layer in a semiconductor manufacturing process, for example raised source/drain applications in CMOS technologies, are presented. These methods and systems provide the capability to measure the thickness of an SEG film in-situ utilizing optical ellipsometry equipment during or after SEG layer growth, prior to removing the wafer from the SEG growth tool. Optical ellipsometry equipment can be integrated into the SEG platform and control software, thus providing automated process control (APC) capability for SEG thickness. The integration of the ellipsometry equipment may be varied, dependent upon the needs of the fabrication facility, e.g., integration to provide ellipsometer monitoring of a single process tool, or multiple tool monitoring, among other configurations.

    摘要翻译： 提出了在半导体制造工艺中允许厚度控制选择性外延生长（SEG）层的方法和系统，例如CMOS技术中的升高的源/漏应用。 这些方法和系统提供了在从SEG生长工具移除晶片之前在SEG层生长期间或之后使用光学椭偏仪设备原位测量SEG膜的厚度的能力。 光学椭圆测量设备可以集成到SEG平台和控制软件中，从而为SEG厚度提供自动化过程控制（APC）能力。 椭圆测量设备的集成可以根据制造设施的需要而变化，例如集成以提供单个处理工具的椭偏仪监控，或者多个工具监视以及其他配置。