SYSTEM AND METHOD FOR ESTIMATION OF INTEGRATED CIRCUIT SIGNAL CHARACTERISTICS USING OPTICAL MEASUREMENTS
    31.
    发明申请
    SYSTEM AND METHOD FOR ESTIMATION OF INTEGRATED CIRCUIT SIGNAL CHARACTERISTICS USING OPTICAL MEASUREMENTS 有权
    使用光学测量估计集成电路信号特性的系统和方法

    公开(公告)号:US20080204057A1

    公开(公告)日:2008-08-28

    申请号:US12115658

    申请日:2008-05-06

    IPC分类号: G01R31/00

    CPC分类号: G01R31/311 Y10T29/49004

    摘要: Systems and methods for making electrical measurements using optical emissions include positioning a sensor/photodetector to measure radiation emissions from devices to be tested. Radiation emission information is collected from the device to be tested during electrical operation. Characteristic features of the radiation emission information are determined, and differences between the characteristic features are deciphered. Based on the differences, models are employed to determine electrical properties of the device, especially operational characteristics.

    摘要翻译: 使用光学发射进行电气测量的系统和方法包括定位传感器/光电检测器以测量待测装置的辐射发射。 在电气操作期间,从要测试的设备收集辐射发射信息。 确定辐射发射信息的特征,特征特征之间的差异被解密。 基于差异,使用模型来确定装置的电气特性,特别是操作特性。

    System and method for estimation of integrated circuit signal characteristics using optical measurements
    33.
    发明授权
    System and method for estimation of integrated circuit signal characteristics using optical measurements 有权
    使用光学测量估计集成电路信号特性的系统和方法

    公开(公告)号:US07378859B2

    公开(公告)日:2008-05-27

    申请号:US11049324

    申请日:2005-02-02

    IPC分类号: G01R31/00

    CPC分类号: G01R31/311 Y10T29/49004

    摘要: Systems and methods for making electrical measurements using optical emissions include positioning a sensor/photodetector to measure radiation emissions from devices to be tested. Radiation emission information is collected from the device to be tested during electrical operation. Characteristic features of the radiation emission information are determined, and differences between the characteristic features are deciphered. Based on the differences, models are employed to determine electrical properties of the device, especially operational characteristics.

    摘要翻译: 使用光学发射进行电气测量的系统和方法包括定位传感器/光电检测器以测量待测装置的辐射发射。 在电气操作期间,从要测试的设备收集辐射发射信息。 确定辐射发射信息的特征,并对特征特征之间的差异进行解密。 基于差异,使用模型来确定装置的电气特性,特别是操作特性。

    Optical trigger for PICA technique
    34.
    发明授权
    Optical trigger for PICA technique 失效
    PICA技术的光触发器

    公开(公告)号:US07239157B2

    公开(公告)日:2007-07-03

    申请号:US11098850

    申请日:2005-04-05

    IPC分类号: G01R31/302

    CPC分类号: G01R31/31709 G01R31/311

    摘要: Optical triggering system and method for synchronizing a test of an integrated circuit chip with its operation. An optical triggering system includes a testing mechanism, such as a PICA testing mechanism, for testing an integrated circuit chip. An optical trigger mechanism generates an optical trigger signal for synchronizing a test of the integrated circuit chip with its operation. The optical trigger mechanism provides an optical trigger signal having reduced jitter and a higher frequency rate than an electrical trigger signal resulting in a more accurate test of the integrated circuit chip.

    摘要翻译: 用于使集成电路芯片的测试与其操作同步的光触发系统和方法。 光触发系统包括用于测试集成电路芯片的诸如PICA测试机构的测试机构。 光学触发机构产生用于使集成电路芯片的测试与其操作同步的光学触发信号。 光学触发机构提供具有比电触发信号更少的抖动和更高频率的光学触发信号,导致集成电路芯片的更准确的测试。

    Method and apparatus for light-controlled circuit characterization

    公开(公告)号:US20060164113A1

    公开(公告)日:2006-07-27

    申请号:US11044943

    申请日:2005-01-27

    IPC分类号: G01R31/02

    CPC分类号: G01R31/311

    摘要: Light-controlled circuit characterization techniques are disclosed. For example, a technique for testing an integrated circuit includes the following steps/operations. At least a portion of the integrated circuit is stimulated with a light source so as to affect one or more electrical characteristics associated with the integrated circuit. By way of example, the light source may be a laser. Optical emissions are captured from the portion of the integrated circuit stimulated by the light source and/or one or more portions of the integrated circuit associated with the stimulated portion. The optical emissions are associated with one or more switching operations of one or more components of the integrated circuit. At least a portion of the captured optical emissions are processed to provide information about the integrated circuit.

    INTEGRATED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY TESTING
    36.
    发明申请
    INTEGRATED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY TESTING 审中-公开
    集成时间依赖电介质断开可靠性测试

    公开(公告)号:US20140207396A1

    公开(公告)日:2014-07-24

    申请号:US13544080

    申请日:2012-07-09

    IPC分类号: G01R31/28

    摘要: Systems for reliability testing include a picometer configured to measure a leakage current across a device under test (DUT); a camera configured to measure optical emissions from the DUT based on a timing of the measurement of the leakage current; and a test system configured to apply a stress voltage to the DUT and to correlate the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

    摘要翻译: 用于可靠性测试的系统包括配置成测量被测器件(DUT)上的漏电流的波长计; 配置为基于所述泄漏电流的测量的定时来测量来自所述DUT的光发射的照相机; 以及被配置为向DUT施加应力电压并且使用处理器将泄漏电流与光发射相关联的测试系统,以通过定位泄漏电流中增加的噪声的实例来确定DUT内的缺陷发生的时间和位置, 在时间上对应于增加的光发射的情况。

    Navigating Analytical Tools Using Layout Software
    37.
    发明申请
    Navigating Analytical Tools Using Layout Software 有权
    使用布局软件导航分析工具

    公开(公告)号:US20130061199A1

    公开(公告)日:2013-03-07

    申请号:US13611776

    申请日:2012-09-12

    IPC分类号: G06F17/50

    摘要: A background process installs a system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook, and current layout coordinates are read from the integrated circuit chip layout display software. A representation of the current layout coordinates is entered into tool control software configured to control a physical tool for analyzing integrated circuits, and the physical tool is controlled with the tool control software. In an “inverse” approach, a background process is used to install at least one system hook for message interception of tool control software configured to control a physical tool for analyzing integrated circuits, and a call message is intercepted through the system hook. Current coordinates are read from the tool control software. A representation of the current coordinates is entered into integrated circuit chip layout display software, and at least a portion of an integrated circuit layout is displayed.

    摘要翻译: 背景过程安装了用于消息拦截集成电路芯片布局显示软件的系统挂钩。 通过系统挂钩截取通话消息,从集成电路芯片布局显示软件中读取当前布局坐标。 将当前布局坐标的表示输入到被配置为控制用于分析集成电路的物理工具的工具控制软件中,并且物理工具由工具控制软件控制。 在逆向方法中,使用后台处理来安装至少一个用于消息拦截的系统钩子,用于控制用于分析集成电路的物理工具的工具控制软件,并且通过系统钩子拦截呼叫消息。 从刀具控制软件读取当前坐标。 将当前坐标的表示输入到集成电路芯片布局显示软件中,并且显示集成电路布局的至少一部分。

    Navigating analytical tools using layout software
    38.
    发明授权
    Navigating analytical tools using layout software 有权
    使用布局软件浏览分析工具

    公开(公告)号:US08312413B2

    公开(公告)日:2012-11-13

    申请号:US12692198

    申请日:2010-01-22

    IPC分类号: G06F17/50 G06F9/44

    摘要: A background process is used to install at least one system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook, and, responsive to the call message, current layout coordinates are read from the integrated circuit chip layout display software. A representation of the current layout coordinates is entered into tool control software configured to control a physical tool for analyzing integrated circuits, and the physical tool is controlled with the tool control software, based on the representation of the current layout coordinates. In an “inverse” approach, a background process is used to install at least one system hook for message interception of tool control software configured to control a physical tool for analyzing integrated circuits, and a call message is intercepted through the system hook. Responsive to the call message, current coordinates are read from the tool control software. A representation of the current coordinates is entered into integrated circuit chip layout display software, and at least a portion of an integrated circuit layout, corresponding to the representation of the current coordinates from the tool control software, is displayed.

    摘要翻译: 后台进程用于安装至少一个系统挂钩,用于消息拦截集成电路芯片布局显示软件。 通过系统挂钩拦截呼叫消息,并响应于呼叫消息,从集成电路芯片布局显示软件读取当前布局坐标。 将当前布局坐标的表示输入到被配置为控制用于分析集成电路的物理工具的工具控制软件中,并且基于当前布局坐标的表示,通过工具控制软件来控制物理工具。 在逆向方法中,使用后台处理来安装至少一个用于消息拦截的系统钩子,用于控制用于分析集成电路的物理工具的工具控制软件,并且通过系统钩子拦截呼叫消息。 响应于通话消息,从工具控制软件读取当前坐标。 将当前坐标的表示输入到集成电路芯片布局显示软件中,并且显示对应于来自刀具控制软件的当前坐标的表示的集成电路布局的至少一部分。

    Self-Adjusting Critical Path Timing of Multi-Core VLSI Chip
    39.
    发明申请
    Self-Adjusting Critical Path Timing of Multi-Core VLSI Chip 有权
    多核VLSI芯片的自调节关键路径时序

    公开(公告)号:US20110296266A1

    公开(公告)日:2011-12-01

    申请号:US12788987

    申请日:2010-05-27

    摘要: A method for adjusting timing of multiple cores within an integrated circuit includes selecting a reference core and a target core from among a plurality of cores of an integrated circuit. Self-test circuitry of the integrated circuit is used to generate a response signature for each of the reference core and the target core. The response signature of the reference core is compared with the response signature of the target core. A local clock buffer of the target core is adjusted until the response signature of the target core matches the response signature of the reference core.

    摘要翻译: 一种用于调整集成电路内的多个核心的定时的方法包括从集成电路的多个核心中选择参考核心和目标核心。 集成电路的自检电路用于为每个参考核心和目标核心产生响应特征。 将参考核心的响应签名与目标核心的响应签名进行比较。 调整目标核心的本地时钟缓冲器,直到目标核心的响应签名与参考核心的响应签名相匹配。

    METHOD AND SYSTEM FOR QUICKLY IDENTIFYING CIRCUIT COMPONENTS IN AN EMISSION IMAGE
    40.
    发明申请
    METHOD AND SYSTEM FOR QUICKLY IDENTIFYING CIRCUIT COMPONENTS IN AN EMISSION IMAGE 有权
    在排放图像中快速识别电路组件的方法和系统

    公开(公告)号:US20110280468A1

    公开(公告)日:2011-11-17

    申请号:US12778544

    申请日:2010-05-12

    IPC分类号: G06T7/00 G01R31/303

    摘要: A system and method for localization and resolvability of an integrated circuit includes selecting one or more electrical stimuli to be applied to a device under test such that the electrical stimuli are chosen to provide a baseline image and a distinguishing image effect as a result of the chosen stimuli when applied to the device under test. The one or more electrical stimuli are applied to the device under test. Emissions from the device under test are measured to provide a measurement data set from the one or more electrical stimuli using one or more measurement tools for collecting the baseline image and the distinguishing image effect. The measurement data set is analyzed to localize and evaluate circuit structures by comparing the baseline image and the distinguishing image effect.

    摘要翻译: 用于集成电路的定位和可解析性的系统和方法包括选择要施加到被测器件的一个或多个电刺激,使得选择电刺激以提供基线图像和作为所选择的结果的结果的区别图像效果 当被施加到被测设备时刺激。 一个或多个电刺激被施加到被测设备。 测量来自被测器件的发射,以使用一个或多个测量工具从一个或多个电刺激提供测量数据集,用于收集基线图像和区分图像效果。 分析测量数据集,通过比较基线图像和区分图像效果来定位和评估电路结构。