公开(公告)号：US20170359027A1

公开(公告)日：2017-12-14

申请号：US15638329

申请日：2017-06-29

Applicant: Rambus Inc.

Inventor： Mohammad Hekmat ,  Reza Navid

IPC: H03B27/00 ,  H03L7/099 ,  H03L7/23 ,  H03L7/06

Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.

公开(公告)号：US20160241191A1

公开(公告)日：2016-08-18

申请号：US15049517

申请日：2016-02-22

Applicant: Rambus Inc.

Inventor： Mohammad Hekmat ,  Farshid Aryanfar ,  Kambiz Kaviani

IPC: H03B27/00 ,  H01F27/28 ,  H03B15/00 ,  H03K5/145 ,  H03B5/12

CPC classification number: H03B27/00 ,  H01F27/006 ,  H01F27/2804 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B15/00 ,  H03K5/145 ,  H03K5/24 ,  H03K2005/00052

Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.

Abstract translation: 耦合多电感及其应用。 一种装置包括几个电路级。 每个电路级包括与其相邻电路级的电感元件重叠的电感元件，形成耦合电路级的回路。 该装置可以是例如具有彼此磁耦合的多个振荡器的多相振荡器，用于在不同相位产生振荡信号。 该装置也可以是例如用于组合输入信号的相位插值器。

公开(公告)号：US20150212953A1

公开(公告)日：2015-07-30

申请号：US14683080

申请日：2015-04-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/16 ,  G11C7/10 ,  G11C5/02

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/02 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract translation: 半导体存储器系统包括第一半导体存储器管芯和第二半导体存储器管芯。 第一半导体存储器管芯包括主数据接口，用于在写操作期间接收输入数据流，并将输入数据流反序列化为第一多个数据流，并且还包括耦合到主数据接口的辅数据接口， 发送第一多个数据流。 第二半导体存储器管芯包括耦合到第一半导体存储器管芯的次级数据接口的次级数据接口，以接收第一多个数据流。