公开(公告)号：US09712373B1

公开(公告)日：2017-07-18

申请号：US13797700

申请日：2013-03-12

Applicant: Rambus Inc.

Inventor： Christopher Haywood

IPC: H04L29/08 ,  G06F13/40 ,  G06F13/28 ,  G06F13/42

CPC classification number: H04L29/08027 ,  G06F13/28 ,  G06F13/4027 ,  G06F13/4282 ,  H04L41/0806 ,  H04L69/324

Abstract: Embodiments of the present invention are directed to memories used in server applications. More specifically, embodiments of the present invention provide a server that has memory management module that is connected to the processor using one or more DDR channels. The memory management module is configured to provide the processor local access and network access to memories on a network. There are other embodiments as well.

公开(公告)号：US12299285B2

公开(公告)日：2025-05-13

申请号：US18218831

申请日：2023-07-06

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood ,  Craig E. Hampel

IPC: G06F3/06

Abstract: A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a request from at least one host. The request includes at least one command to perform a memory compression operation on first uncompressed data that is stored in a first memory region. Compression circuitry, in response to the at least one command, compresses the first uncompressed data to first compressed data. The first compressed data is transferred to a second memory region.

公开(公告)号：US12164447B2

公开(公告)日：2024-12-10

申请号：US18116266

申请日：2023-03-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Christopher Haywood

IPC: G06F13/16 ,  G06F13/40 ,  G11C5/04 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4096

Abstract: In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.

公开(公告)号：US11914863B2

公开(公告)日：2024-02-27

申请号：US17860773

申请日：2022-07-08

Applicant: Rambus Inc.

Inventor： Christopher Haywood

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673

Abstract: A serial data buffer integrated circuit comprises unidirectional host-side input and output ports, and unidirectional memory-side input and output ports. Scheduling logic generates memory device commands for writing to and reading from a memory device based on a set of host-side input packets received from a memory controller. A unidirectional serial host side input port receives host-side input packets from the memory controller. A unidirectional serial memory side output port transmits the memory device commands and the write data to the memory device based on the scheduled timing. A unidirectional serial memory side input port receives read data from the memory device in response to a read command, and a unidirectional serial host side output port transmits the read data to the memory controller within the timing constraints of the memory device.

公开(公告)号：US11841793B2

公开(公告)日：2023-12-12

申请号：US17580427

申请日：2022-01-20

Applicant: Rambus Inc.

Inventor： Steven C. Woo ,  Christopher Haywood ,  Evan Lawrence Erickson

IPC: G06F12/02 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/0811

CPC classification number: G06F12/0238 ,  G06F12/0811 ,  G06F12/0871 ,  G06F12/0882

Abstract: Computing devices, methods, and systems for switch-based free memory tracking in data center environments are disclosed. An exemplary switch integrated circuit (IC), which is used in a switched fabric or a network, can include a processing device and a tracking structure that is distributed with at least a second switch IC. The tracking structure tracks free memory units that are accessible in a first set of nodes by the second switch IC. The processing device receives a request for a number of free memory units. The processing device forwards the request to a node in the first set of nodes that has at least the number of free memory units or forwards the request to the second switch IC that has at least the number of free memory units or responds to the request with a response that indicates that the request could not be fulfilled.

公开(公告)号：US11803323B2

公开(公告)日：2023-10-31

申请号：US17608426

申请日：2020-04-28

Applicant: RAMBUS INC.

Inventor： Christopher Haywood ,  Frederick A. Ware

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0673

Abstract: A cascaded memory system includes a memory module having a primary interface coupled to a memory controller via a first communication channel and a secondary interface coupled to a second memory module via a second communication channel. The first memory module buffers and repeats signals received on the primary and secondary interfaces to enable communications between the memory controller and the secondary memory module.

公开(公告)号：US20230333989A1

公开(公告)日：2023-10-19

申请号：US18139220

申请日：2023-04-25

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood ,  Mark D. Kellam

IPC: G06F12/1009 ,  G06F13/16 ,  G06F12/0804 ,  G06F12/123 ,  G06F12/0882

CPC classification number: G06F12/1009 ,  G06F13/1668 ,  G06F12/0804 ,  G06F12/123 ,  G06F12/0882 ,  G06F2212/7201

Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.

公开(公告)号：US20230305891A1

公开(公告)日：2023-09-28

申请号：US18094474

申请日：2023-01-09

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  Evan Lawrence Erickson

IPC: G06F9/50 ,  G06F9/451 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1072

CPC classification number: G06F9/5016 ,  G06F9/452 ,  G06F9/5077 ,  G06F12/0238 ,  G06F12/1009 ,  G06F12/1072 ,  G06F2212/7201

Abstract: A memory allocation device for deployment within a host server computer includes control circuitry, a first interface to a local processing unit disposed within the host computer and local operating memory disposed within the host computer, and a second interface to a remote computer. The control circuitry allocates a first portion of the local memory to a first process executed by the local processing unit and transmits, to the remote computer via the second interface, a request to allocate to a second process executed by the local processing unit a first portion of a remote memory disposed within the remote computer. The control circuitry further receives instructions via the first interface to store data at a memory address within the first portion of the remote memory and transmits those instructions to the remote computer via the second interface.

公开(公告)号：US11567679B2

公开(公告)日：2023-01-31

申请号：US17333409

申请日：2021-05-28

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood

IPC: G06F3/06

Abstract: A memory allocation device on an originating node requests an allocation of memory from a remote node. In response, the memory allocation device on the remote node returns a global system address that can be used to access the remote allocation from the originating node. Concurrent with the memory allocation device assigning (associating) a local (to its node) physical address to be used to access the remote allocation, the remote node allocates local physical memory to fulfill the remote allocation request. In this manner, the remote node has already completed the overhead operations associated with the remote allocation requested by the time the remote allocation is accessed by the originating node.

公开(公告)号：US20220179799A1

公开(公告)日：2022-06-09

申请号：US17543449

申请日：2021-12-06

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood ,  Mark D. Kellam

IPC: G06F12/1009 ,  G06F12/0882 ,  G06F12/0804 ,  G06F12/123 ,  G06F13/16

Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.