公开(公告)号：US20130279280A1

公开(公告)日：2013-10-24

申请号：US13865110

申请日：2013-04-17

Applicant: RAMBUS INC.

Inventor： Paul Damian Franzon ,  Evan Lawrence Erickson ,  Thomas Vogelsang ,  Frederick A. Ware

IPC: G11C29/04

CPC classification number: G11C29/04 ,  G11C29/702 ,  G11C29/808

Abstract: A memory device includes a stack of circuit layers, each circuit layer having formed thereon a memory circuit configured to store data and a redundant resources circuit configured to provide redundant circuitry to correct defective circuitry on at least one memory circuit formed on at least one layer in the stack. The redundant resources circuit includes a partial bank of redundant memory cells, wherein an aggregation of the partial bank of redundant memory cells in each of the circuit layers of the stack includes at least one full bank of redundant memory cells and wherein the redundant resources circuit is configured to replace at least one defective bank of memory cells formed on any of the circuit layers in the stack with at least a portion of the partial bank of redundant memory cells formed on any of the circuit layers in the stack.

Abstract translation: 存储器件包括电路层堆叠，每个电路层上形成有存储器电路，其被配置为存储数据，冗余资源电路被配置为提供冗余电路以校正在至少一个层上形成的至少一个存储器电路上的有缺陷的电路 堆栈。 所述冗余资源电路包括冗余存储器单元的部分组，其中所述堆叠的每个电路层中的冗余存储器单元的部分组的聚集包括至少一个全部冗余存储器单元，并且其中所述冗余资源电路为 被配置为替换形成在堆叠中的任何电路层上的至少一个存储单元的至少一个有缺陷的存储单元组，其中所述冗余存储器单元的部分库的至少一部分形成在堆叠中的任何电路层上。

公开(公告)号：US20250117138A1

公开(公告)日：2025-04-10

申请号：US18906976

申请日：2024-10-04

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Taeksang Song

IPC: G06F3/06

Abstract: Disclosed are techniques for a memory buffer to track access to paged regions of a memory system at a configurable granularity finer than the size of the paged regions to provide more detailed statistics on memory access. The memory buffer may advertise its capabilities for fine-grained cold page tracking. The memory buffer may receive from the host information to configure a granularity of sub-regions of a paged region and a size of counters used to track access to the sub-regions. The memory buffer may track access requests to the sub-regions using the counters and to provide information on sub-region tracking to the host to identify individual hot or cold sub-regions. The host may make migration decisions for the paged regions with more granular information such as compaction of sub-regions to create a cold page or to treat each sub-region as a separately compressible entity to compress a mostly cold page.

公开(公告)号：US20250053521A1

公开(公告)日：2025-02-13

申请号：US18786296

申请日：2024-07-26

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson

IPC: G06F13/16 ,  G06F12/02 ,  G06F13/42

Abstract: A memory system selectively compresses and/or decompresses pages of a memory array based on requests from a host device. Upon performing compression, the memory buffer device returns compression context metadata to the host device for storing in the page table of the host device to enable the host device to subsequently obtain data from the compressed page. The host device may subsequently send a request for the memory buffer device to perform decompression to a free page in the memory array for accessing by the host device, or the host device may directly access the compressed page for local decompression and storage.

公开(公告)号：US12174749B2

公开(公告)日：2024-12-24

申请号：US17576398

申请日：2022-01-14

Applicant: Rambus Inc.

Inventor： Steven C. Woo ,  Christopher Haywood ,  Evan Lawrence Erickson

IPC: G06F12/10 ,  G06F9/455 ,  G06F12/02 ,  G06F12/0882 ,  G06F12/1009

Abstract: The creation, maintenance, and accessing of page tables is done by a virtual machine monitor running on a computing system rather than the guest operating systems. This allows page table walks to be completed in fewer memory accesses when compared to the guest operating system's maintenance of the page tables. In addition, the virtual machine monitor may utilize additional resources to offload page table access and maintenance functions from the CPU to another device, such as a page table management device or page table management node. Offloading some or all page table access and maintenance functions to a specialized device or node enables the CPU to perform other tasks during page table walks and/or other page table maintenance functions.

公开(公告)号：US12130772B2

公开(公告)日：2024-10-29

申请号：US17971964

申请日：2022-10-24

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Evan Lawrence Erickson

IPC: G06F15/78 ,  G06F21/72

CPC classification number: G06F15/7807 ,  G06F21/72

Abstract: A multi-processor device is disclosed. The multi-processor device includes interface circuitry to receive requests from at least one host device. A primary processor is coupled to the interface circuitry to process the requests in the absence of a failure event associated with the primary processor. A secondary processor processes operations on behalf of the primary processor and selectively receives the requests from the interface circuitry based on detection of the failure event associated with the primary processor.

公开(公告)号：US20240194231A1

公开(公告)日：2024-06-13

申请号：US18531543

申请日：2023-12-06

Applicant: Rambus Inc.

Inventor： Taeksang Song ,  Evan Lawrence Erickson ,  Steven C. Woo

IPC: G11C7/10 ,  G11C7/24

CPC classification number: G11C7/1069 ,  G11C7/1039 ,  G11C7/1063 ,  G11C7/24

Abstract: A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a read command to retrieve read data from a memory. Memory interface circuitry couples to the memory. Data freshness authentication circuitry performs a freshness verification operation on the read data. Read data forwarding circuitry, in a skid mode of operation, transmits the read data to the host prior to completion of the freshness verification operation.

公开(公告)号：US20240160388A1

公开(公告)日：2024-05-16

申请号：US18497860

申请日：2023-10-30

Applicant: Rambus Inc.

Inventor： Taeksang Song ,  Evan Lawrence Erickson ,  Wendy Elsasser

IPC: G06F3/06

CPC classification number: G06F3/0689 ,  G06F3/0623 ,  G06F3/0656 ,  G06F3/0659

Abstract: A memory buffer device facilitates secure read and write operations associated with data that includes a predefined data pattern. For read operations, the memory buffer device detects a read data pattern in the read data that matches a predefined data pattern. The memory buffer device may then generate a read response that includes metadata identifying the read data pattern without sending the read data itself. The memory buffer device may also receive Write Request without Data (RwoD) commands from the host that include metadata identifying a write data pattern. The memory buffer device identifies the associated data pattern and writes the data pattern or the metadata to the memory array. The memory buffer device may include encryption and decryption logic for communicating the metadata in encrypted form.

公开(公告)号：US20230350603A1

公开(公告)日：2023-11-02

申请号：US18139190

申请日：2023-04-25

Applicant: Rambus Inc.

Inventor： Taeksang Song ,  Evan Lawrence Erickson ,  Craig E. Hampel

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0622 ,  G06F3/0679

Abstract: Technologies for securing dynamic random access memory contents to nonvolatile memory in a persistent memory module are described. One persistent memory module includes an inline memory encryption (IME) circuit that receives a data stream from a host, encrypts the data stream into encrypted data, and stores the encrypted data in DRAM. A management processor transfers the encrypted data from the DRAM to persistent storage memory responsive to a signal associated with a power-loss or power-down event.

公开(公告)号：US11663138B2

公开(公告)日：2023-05-30

申请号：US17543449

申请日：2021-12-06

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood ,  Mark D. Kellam

IPC: G06F12/10 ,  G06F12/1009 ,  G06F13/16 ,  G06F12/0804 ,  G06F12/123 ,  G06F12/0882

CPC classification number: G06F12/1009 ,  G06F12/0804 ,  G06F12/0882 ,  G06F12/123 ,  G06F13/1668 ,  G06F2212/7201

Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.

公开(公告)号：US20230163964A1

公开(公告)日：2023-05-25

申请号：US17990417

申请日：2022-11-18

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Joel Wittenauer ,  Winthrop John Wu

IPC: H04L9/08

CPC classification number: H04L9/0877 ,  H04L9/0816

Abstract: An integrated circuit comprises an interface controller to receive a message, wherein at least a portion of the message is encrypted, a primary processor coupled to the interface controller and configured to process the received message, and a secondary secure processor coupled to the primary processor and to the interface controller. The secondary secure processor is configured to decrypt the portion of the message that is encrypted on behalf of the primary processor, analyze the decrypted portion of the message to determine whether the decrypted portion comprises information pertaining to sensitive data, and responsive to determining that the decrypted portion comprises information pertaining to sensitive data, process the information pertaining to the sensitive data and provide the sensitive data to the interface controller via a secure private bus not accessible by the primary processor.