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公开(公告)号：US06418513B1
公开(公告)日：2002-07-09
申请号：US09340077
申请日：1999-06-25
IPC分类号： G06F1200
CPC分类号： G06F12/0897
摘要： A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.
摘要翻译： 一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。 将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。 使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。 然后可能不精确地重新加载上级（L1）高速缓存（高级缓存也可以不精确地用存储指令重新加载）。 低级（L2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（ 基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。 本发明可以应用于例如指令，操作数数据和翻译高速缓存。
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32.发明授权Layered local cache with lower level cache optimizing allocation mechanism 有权分层本地缓存，具有较低级别的缓存优化分配机制公开(公告)号：US06970976B1
公开(公告)日：2005-11-29
申请号：US09340074
申请日：1999-06-25
CPC分类号： G06F12/0897 , G06F12/0831 , G06F12/0859 , G06F12/1027
摘要： A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (Li) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.
摘要翻译： 一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。 将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。 使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。 然后可能不精确地重新加载上层（Li）高速缓存（上级缓存也可能不精确地用存储指令重新加载）。 低级（L2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（ 基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。 本发明可以应用于例如指令，操作数数据和翻译高速缓存。
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33.发明授权Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem 失效一种通过可重配置散列存储子系统在数据处理系统内提供高可用性的方法公开(公告)号：US06823471B1
公开(公告)日：2004-11-23
申请号：US09364281
申请日：1999-07-30
IPC分类号： G06F1100
CPC分类号： G06F11/20
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing a respective one of a plurality of data streams. If an error is detected in a particular hardware partition, the data stream assigned to that hardware partition is reassigned to another of the plurality of hardware partitions, thus preventing an error in one of the hardware partitions from resulting in a catastrophic failure.
摘要翻译： 处理器包括执行资源，数据存储和指令排序单元，其耦合到执行资源和数据存储器，其将数据存储器内的指令提供给执行资源。 执行资源，数据存储和指令排序单元中的至少一个由具有用于处理多个数据流中的相应一个的类似功能的多个硬件分区来实现。 如果在特定硬件分区中检测到错误，则分配给该硬件分区的数据流被重新分配给多个硬件分区中的另一个，从而防止其中一个硬件分区中的错误导致灾难性故障。
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34.发明授权Address dependent caching behavior within a data processing system having HSA (hashed storage architecture) 失效具有HSA（散列存储架构）的数据处理系统中的依赖于地址的缓存行为公开(公告)号：US06446165B1
公开(公告)日：2002-09-03
申请号：US09364287
申请日：1999-07-30
IPC分类号： G06F1300
CPC分类号： G06F12/0811
摘要： A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, each store only data having associated addresses within a respective one of a plurality of subsets of an address space and implement diverse caching behaviors. The diverse caching behaviors can include differing memory update policies, differing coherence protocols, differing prefetch behaviors, and differing cache line replacement policies.
摘要翻译： 处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和在同一级别的多个高速缓存。 存储由执行单元使用的数据的高速缓存仅存储具有地址空间的多个子集中的相应地址内的相关联地址的数据，并且实现多种缓存行为。 不同的缓存行为可以包括不同的内存更新策略，不同的一致性协议，不同的预取行为以及不同的缓存行替换策略。
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35.发明授权公开(公告)号：US06516404B1
公开(公告)日：2003-02-04
申请号：US09364283
申请日：1999-07-30
IPC分类号： G06F1200
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/30138 , G06F9/3016 , G06F9/384 , G06F12/06 , G06F12/0846
摘要： A processor having a hashed and partitioned register file includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of registers coupled to the execution unit. The plurality of registers are partitioned into a plurality of groups, such that registers within each group can store only data having associated addresses within a respective one of a plurality of subsets of an address space.
摘要翻译： 具有散列和分区寄存器文件的处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和耦合到执行单元的多个寄存器。 多个寄存器被划分成多个组，使得每个组中的寄存器可以仅存储具有地址空间的多个子集中的相应地址内的相关联地址的数据。
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36.发明授权Layered local cache with lower level cache updating upper and lower level cache directories 失效具有较低级别缓存的分层本地缓存更新上下级缓存目录公开(公告)号：US06463507B1
公开(公告)日：2002-10-08
申请号：US09340082
申请日：1999-06-25
IPC分类号： G06F1200
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0831 , G06F12/1027
摘要： A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.
摘要翻译： 一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。 将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。 使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。 然后可能不精确地重新加载上级（L1）高速缓存（高级缓存也可以不精确地用存储指令重新加载）。 低级（L2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（ 基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。 本发明可以应用于例如指令，操作数数据和翻译高速缓存。
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37.发明授权Method and system for managing speculative requests in a multi-level memory hierarchy 失效用于管理多层内存层次结构中的推测性请求的方法和系统公开(公告)号：US06418516B1
公开(公告)日：2002-07-09
申请号：US09364409
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1208
CPC分类号： G06F9/30047 , G06F9/3804 , G06F9/383 , G06F9/3842 , G06F12/0862 , G06F12/0897
摘要： A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions and treats instructions in a different manner when they are loaded speculatively. These prefetch requests can be demand load requests, where the processing unit will need the operand data or instructions, or speculative load requests, where the processing unit may or may not need the operand data or instructions, but a branch prediction or stream association predicts that they might be needed. The load requests are sent to the lower level cache when the upper level cache does not contain the value required by the load. If a speculative request is for an instruction which is likewise not present in the lower level cache, that request is ignored, keeping both the lower level and upper level caches free of speculative values that are infrequently used. If the value is present in the lower level cache, it is loaded into the upper level cache. If a speculative request is for operand data, the value is loaded only into the lower level cache if it is not already present, keeping the upper level cache free of speculative operand data.
摘要翻译： 一种操作计算机系统的多级存储器层级的方法和体现该方法的装置，其中指令从直接从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。 本发明适用于作为操作数数据或指令的值，并且当它们被推测地加载时以不同的方式对待指令。 这些预取请求可以是需求负载请求，其中处理单元将需要操作数数据或指令或推测性负载请求，其中处理单元可能需要或可能不需要操作数数据或指令，但分支预测或流关联预测 他们可能需要。 当高级缓存不包含负载所需的值时，负载请求将发送到较低级别的缓存。 如果对低级缓存中同样不存在的指令进行推测性请求，则忽略该请求，同时保持较低级别和上级缓存都不会被不经常使用的推测值。 如果该值存在于较低级缓存中，则将其加载到上级缓存中。 如果对于操作数数据是推测性请求，则该值仅在尚未存在的情况下被加载到较低级别的高速缓存中，保持高级缓存没有推测操作数数据。
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38.发明授权Processor assigning data to hardware partition based on selectable hash of data address 失效处理器根据数据地址的可选哈希分配数据到硬件分区公开(公告)号：US06470442B1
公开(公告)日：2002-10-22
申请号：US09364286
申请日：1999-07-30
IPC分类号： B06F1576
CPC分类号： G06F9/3891 , G06F9/3012 , G06F9/3013 , G06F9/3802 , G06F9/384 , G06F9/3885 , G06F15/7857
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing data. The data processed by each hardware partition is assigned according to a selectable hash of addresses associated as with the data. In a preferred embodiment, the selectable hash can be altered dynamically during the operation of the processor, for example, in response to detection of an error or a load imbalance between the hardware partitions.
摘要翻译： 处理器包括执行资源，数据存储和指令排序单元，其耦合到执行资源和数据存储器，其将数据存储器内的指令提供给执行资源。 执行资源，数据存储和指令排序单元中的至少一个用多个用于处理数据的相同功能的硬件分区来实现。 由每个硬件分区处理的数据根据与数据相关联的地址的可选择的散列来分配。 在优选实施例中，可以在处理器的操作期间动态地改变可选择的散列，例如响应于硬件分区之间的错误或负载不平衡的检测。
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39.发明授权Method for upper level cache victim selection management by a lower level cache 失效低级缓存的上级缓存受害者选择管理方法公开(公告)号：US06446166B1
公开(公告)日：2002-09-03
申请号：US09340073
申请日：1999-06-25
IPC分类号： G06F1214
CPC分类号： G06F12/0811 , G06F12/0897 , G06F12/12
摘要： A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.
摘要翻译： 一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。 将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。 使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。 然后可能不精确地重新加载上级（L1）高速缓存（高级缓存也可以不精确地用存储指令重新加载）。 低级（L2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（ 基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。 本发明可以应用于例如指令，操作数数据和翻译高速缓存。
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40.发明授权Layered local cache mechanism with split register load bus and cache load bus 有权分层本地缓存机制，具有分裂寄存器负载总线和缓存负载总线公开(公告)号：US06405285B1
公开(公告)日：2002-06-11
申请号：US09340076
申请日：1999-06-25
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F12/0897
摘要： A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.
摘要翻译： 一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。 将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。 使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。 然后可能不精确地重新加载上级（L1）高速缓存（高级缓存也可以不精确地用存储指令重新加载）。 低级（L2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（ 基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。 本发明可以应用于例如指令，操作数数据和翻译高速缓存。
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