公开(公告)号：US5844920A

公开(公告)日：1998-12-01

申请号：US745913

申请日：1996-11-07

申请人： Christopher P. Zook ,  Neal Glover ,  Alan J. Armstrong

发明人： Christopher P. Zook ,  Neal Glover ,  Alan J. Armstrong

IPC分类号： G11B5/012 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  G11B20/10

CPC分类号： G11B20/1217 ,  G11B20/1426 ,  G11B20/1813 ,  G11B27/3027 ,  G11B5/012 ,  G11B2020/1476 ,  G11B2220/20

摘要： A magnetic disk storage system is disclosed wherein byte synchronization to sector data is achieved even when noise in the read channel, due for instance to a thermal asperity (TA), corrupts the primary preamble and/or sync mark fields or causes a loss of frequency or phase lock. The data sector format is modified to comprise at least one secondary sync mark in addition to the conventional primary sync mark recorded at the beginning of the data field. In this manner, when the primary sync mark becomes undetectable due to errors, or when byte synchronization is lost, the storage system can still synchronize to the data sector using the secondary sync mark. The secondary sync mark is preferably spaced apart from the primary sync mark with either a gap (no data) or user data inserted inbetween. In the latter embodiment, two methods are employed to recover user data inbetween the primary and secondary sync marks when the primary sync mark is undetectable: on-the-fly erasure pointer error correction, and buffering to facilitate retroactive synchronization. The secondary sync mark may optionally include a secondary preamble to facilitate phase locking to the data when the primary preamble is corrupted by errors. The present invention also provides "split segment" resynchronization for synchronizing a first section of data using a first mark, and retroactively synchronizing a second section of data using a following sync mark when synchronization is lost.

摘要翻译： 公开了一种磁盘存储系统，其中即使由于例如热不平坦（TA）而导致的读通道中的噪声破坏了主前同步码和/或同步标记场，也导致频率损失，实现了与扇区数据的字节同步 或锁相。 修改数据扇区格式，除了在数据字段的开始处记录的常规主同步标记之外还包括至少一个辅助同步标记。 以这种方式，当主同步标记由于错误而变得不可检测，或者当字节同步丢失时，存储系统仍然可以使用辅助同步标记与数据扇区同步。 次同步标记优选地与主同步标记间隔开，间隙（无数据）或插入其间的用户数据。 在后一实施例中，当主同步标记不可检测时，采用两种方法来恢复主同步标记和辅同步标记之间的用户数据：即时擦除指针错误校正和缓冲以便于追溯同步。 辅助同步标记可以可选地包括辅助前同步码，以便在主要前同步码被错误破坏时便于锁定数据。 本发明还提供了用于使用第一标记来同步第一部分数据的“分割段”重新同步，并且当同步丢失时使用后续同步标记追溯地同步第二数据段。

公开(公告)号：US5844919A

公开(公告)日：1998-12-01

申请号：US697686

申请日：1996-09-16

申请人： Neal Glover ,  Christopher P. Zook ,  John Schadegg ,  William L. Witt

发明人： Neal Glover ,  Christopher P. Zook ,  John Schadegg ,  William L. Witt

IPC分类号： G11B20/18 ,  H03M13/15 ,  H03M13/29 ,  H03M13/35 ,  G11C29/00

CPC分类号： G11B20/1883 ,  G11B20/1816 ,  H03M13/151 ,  H03M13/29 ,  H03M13/35 ,  G11B2220/20

摘要： A disc storage system comprising a sector level ECS for correcting errors within a sector during readback, and a track level ECS for correcting a sector that becomes unrecoverable at the sector level either because the number of hard errors exceeds the error correction capability of the sector redundancy, or because the sector is unreadable due, for instance, to an inability to synchronize to the sector data. A data buffer stores the data sectors, and a redundancy buffer stores the track level redundancy data. If during a read operation a data sector is determined to be unrecoverable using the sector level redundancy, the storage system corrects the unrecoverable sector using the track level redundancy.

摘要翻译： 一种盘存储系统，包括用于在回读期间校正扇区内的错误的扇区级ECS，以及用于校正扇区级别变得不可恢复的扇区的轨迹级ECS，这是因为硬错误的数量超过扇区冗余的纠错能力 ，或者因为扇区由于例如无法与扇区数据同步而不可读。 数据缓冲器存储数据扇区，并且冗余缓冲器存储轨道级冗余数据。 如果在读取操作期间使用扇区级冗余确定数据扇区不可恢复，则存储系统使用轨道级冗余来校正不可恢复扇区。

公开(公告)号：US5844911A

公开(公告)日：1998-12-01

申请号：US761993

申请日：1996-12-12

申请人： John Schadegg ,  Neal Glover ,  Laura Droege Shellhamer ,  William L. Witt ,  Richard T. Behrens

发明人： John Schadegg ,  Neal Glover ,  Laura Droege Shellhamer ,  William L. Witt ,  Richard T. Behrens

IPC分类号： G11B7/007 ,  G11B20/18 ,  G01R31/28 ,  G11B7/00

CPC分类号： G11B20/1883 ,  G11B2220/20 ,  G11B7/007

摘要： A defect management system is disclosed for disc storage systems which avoids the access latency associated with conventional linear replacement techniques by dispersing spare segments throughout each track at a regular interval and buffering sectors inbetween a defective sector and the corresponding spare segment during read and write operations. In one embodiment, a spare segment is an entire sector which replaces a defective data sector; and in an alternative embodiment, a spare segment stores only the defective portion of a data sector which is more efficient, but also more complicated in implementation. In both embodiments, the defect management system comprises a defect locator for locating a defective segment within a data sector. Once located, the defect management system maps the defective sector (or the defective portion thereof) to the nearest available spare segment. Then when accessing the track that comprises the defective sector, the data sectors between the defective segment and corresponding spare segment are buffered in a data buffer, and an area in the data buffer is reserved for storing the data associated with the spare segment. In this manner, data can be written to and read from the track in a contiguous sequence without requiring an extra revolution of latency as in the conventional linear replacement defect mapping techniques.

摘要翻译： 公开了一种用于盘存储系统的缺陷管理系统，其避免了与常规线性替换技术相关联的访问延迟，通过以常规间隔分散每个磁道上的备用段，并在读写操作期间缓冲缺陷扇区与相应备用段之间的扇区。 在一个实施例中，备用段是替换有缺陷的数据扇区的整个扇区; 并且在替代实施例中，备用段仅存储更有效的数据扇区的缺陷部分，而且在实现中更复杂。 在两个实施例中，缺陷管理系统包括用于定位数据扇区内的缺陷段的缺陷定位器。 一旦定位，缺陷管理系统将缺陷扇区（或其缺陷部分）映射到最近的可用备用段。 然后，当访问包括缺陷扇区的轨迹时，将缺陷段与相应的备用段之间的数据扇区缓冲在数据缓冲器中，并且数据缓冲区中的区域被保留用于存储与备用段相关联的数据。 以这种方式，可以以连续的顺序将数据写入轨道并从轨道读取数据，而不需要象传统的线性替换缺陷映射技术那样的等待时间的额外旋转。

公开(公告)号：US5701304A

公开(公告)日：1997-12-23

申请号：US714749

申请日：1996-09-16

申请人： Neal Glover ,  Christopher P. Zook ,  John Schadegg ,  William L. Witt

发明人： Neal Glover ,  Christopher P. Zook ,  John Schadegg ,  William L. Witt

IPC分类号： G11B20/18 ,  G06F11/00

CPC分类号： G11B20/1883 ,  G11B20/1803 ,  G11B2020/10916 ,  G11B2220/20

摘要： In a disc drive storage system employing a track level redundancy sector for reconstructing a data sector unrecoverable at the sector level, the latency of the storage system is minimized by performing a write operation according to the following steps: 1. seek to the target track corresponding to the sector(s) to be written; 2. once at the target track, wait for the recording head to reach the first sector in the track (sector 0); 3. begin reading and processing the sectors in the target track to regenerate the redundancy sector; 4. when the recording head reaches the target sector(s), combine the new data sector(s) with the regenerated redundancy sector, switch to a write operation, and write the new sectors to the track; 5. after writing the new data sectors to the track, switch back to a read operation and continue reading the data sectors in the track and combining them with the regenerated redundancy sector; and 6. when the recording head reaches the redundancy sector, which is preferably the last sector on the track, switch to a write operation and write the regenerated redundancy sector to the track.

摘要翻译： 在采用磁道级冗余扇区用于重构在扇区级别不可恢复的数据扇区的磁盘驱动器存储系统中，通过根据以下步骤执行写入操作使存储系统的等待时间最小化：1.寻找对应于 要写入的部门; 2.在目标轨道上，等待记录头到达轨道中的第一扇区（扇区0）; 3.开始读取和处理目标轨道中的扇区，以重新生成冗余扇区; 当记录头到达目标扇区时，将新数据扇区与再生冗余扇区组合，切换到写操作，并将新扇区写入轨道; 在将新的数据扇区写入轨道之后，切换回读操作并继续读取轨道中的数据扇区并将其与再生的冗余扇区组合; 当记录头到达冗余扇区时，优选地是轨道上的最后一个扇区，切换到写操作，并将再生冗余扇区写入轨道。

公开(公告)号：US5384786A

公开(公告)日：1995-01-24

申请号：US679570

申请日：1991-04-02

申请人： Trent Dudley ,  Neal Glover ,  Larry King

发明人： Trent Dudley ,  Neal Glover ,  Larry King

IPC分类号： G06F11/10 ,  H03M13/15 ,  H03M13/00

CPC分类号： G06F11/1076 ,  G06F11/1008 ,  H03M13/151

摘要： Apparatus and methods are disclosed for providing an improved system for identifying the location and value of errors introduced in binary data encoded using Reed-Solomon and related codes and to detect miscorrections of such codes with an auxiliary code. The invention employs an architecture based on a microcode engine that is specialized for error identification and that supports interleaved codewords. This architecture can be efficiently fabricated as an integrated circuit, yet is capable of identifying multiple introduced errors "on the fly" i.e. with performance sufficient to not significantly slow the process of reading from data storage or transmission subsystems such as, but not limited to, optical disks. In the preferred embodiment, a new two-step method of error syndrome computation is employed to reduce circuit cost and complexity. An improved iterative algorithm is provided which reduces circuit cost and complexity and decreases the time required to generate the error locator polynomial. Cyclic redundancy check (CRC) information is adjusted as introduced errors are identified during the Chien search, thus reducing the time required to protect against ECC miscorrection. Externally-specified error thresholds allow detection of excessive numbers of errors.

摘要翻译： 公开了用于提供改进的系统的装置和方法，该系统用于识别使用Reed-Solomon和相关代码编码的二进制数据中引入的误差的位置和值，并且用辅助码来检测这些代码的误差。 本发明采用基于专用于错误识别并支持交错码字的微代码引擎的架构。 该架构可以有效地制造为集成电路，但是能够“即时”地识别多个引入的错误，即具有足以不显着地减慢从数据存储或传输子系统读取的过程的性能，例如但不限于， 光盘。 在优选实施例中，采用新的误差校正计算的两步法来降低电路成本和复杂度。 提供了一种改进的迭代算法，其降低了电路成本和复杂性，并减少了生成误差定位多项式所需的时间。 循环冗余校验（CRC）信息被调整，因为在Chien搜索期间识别出引入的错误，从而减少了防止ECC错误修复所需的时间。 外部指定的错误阈值允许检测到过多的错误。

公开(公告)号：US5329554A

公开(公告)日：1994-07-12

申请号：US879938

申请日：1992-05-08

申请人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

发明人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

IPC分类号： G11B20/10 ,  G11B20/14 ,  H03K5/1532 ,  H03K5/19 ,  H04L25/08 ,  H04L27/00 ,  H04L27/06

CPC分类号： G11B20/10037 ,  G11B20/10009 ,  G11B20/1403 ,  H03K5/19

摘要： Disclosed is a pulse detector that uses four samples of an analog signal to detect a pulse as soon as one sample beyond the time of the peak of the signal level at the pulse. The pulse detector can detect pulses by sampling at the center of a peak of the pulse or by sampling at either side of the peak of the pulse. The pulse detector detects pulses while tracking data, and it uses an alternate detection system for detecting pulses while acquiring timing and gain lock on a signal having a known data pattern. The detector uses either the sampled signal levels directly, or a moving average of two samples to perform the detection.

摘要翻译： 公开了一种使用四个模拟信号样本的脉冲检测器，一旦超过脉冲信号电平峰值时间的一个采样就检测脉冲。 脉冲检测器可以通过在脉冲峰值的中心采样或通过在脉冲峰值的任一侧进行采样来检测脉冲。 脉冲检测器在跟踪数据的同时检测脉冲，并且在采集具有已知数据模式的信号的定时和增益锁定的同时使用用于检测脉冲的替代检测系统。 检测器使用采样信号电平或两个采样的移动平均值进行检测。

公开(公告)号：US5291499A

公开(公告)日：1994-03-01

申请号：US852015

申请日：1992-03-16

申请人： Richard T. Behrens ,  Kent D. Anderson ,  Neal Glover

发明人： Richard T. Behrens ,  Kent D. Anderson ,  Neal Glover

IPC分类号： G06F11/30 ,  G06F11/10 ,  G11B20/14 ,  G11B20/18 ,  H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H03M7/14 ,  H03M13/23 ,  H03M13/41 ,  H04B3/04 ,  H04L25/08 ,  H04L25/49 ,  H04L25/497 ,  H04L27/00 ,  G06F11/00

CPC分类号： G11B20/1426 ,  G11B20/1833 ,  H03M13/41 ,  H03M13/4107 ,  H04L25/4906 ,  H04L25/497

摘要： A Viterbi detector is modified to reduce its implementation complexity. A partial-response signal may be viewed as a sequence of expected samples generated from a finite-state-machine model. In a typical Viterbi demodulator implemented using the add, compare, select (ACS) method, each state in the expected sample sequence model is associated with a hardware module to perform the functions of adding new branch error metrics to path error metrics, comparing path error metrics, and selecting the path having the lowest path error metric. In this invention, an ACS module may have two or more sequence-model states dynamically associated with it, such that at some times one sequence-model state is associated with it and at other times another sequence-model state is associated with it. This reduces the number of ACS modules required and also reduces the size/complexity of the demodulator's path memories which must store one path for each ACS module. Groups of sequence-model states may be chosen to share an ACS module without significant loss in performance as compared to the original, unreduced Viterbi demodulator. The invention supports a wide range of sample models by making the expected sample sequence of an isolated medium transition programmable. The invention reduces the speed at which the detector circuitry must operate relative to the sample rate by allowing multiple samples to be processed simultaneously. Several reduced detectors for specific sample sequence models are presented for particular applications. The invention is applicable to other types of Viterbi detectors, such as decoders for convolutional codes.

摘要翻译： 修改维特比检测器以减少其实现复杂度。 部分响应信号可以被视为从有限状态机模型生成的预期样本的序列。 在使用加法，比较，选择（ACS）方法实现的典型维特比解调器中，预期采样序列模型中的每个状态与硬件模块相关联，以执行向路径误差度量添加新的分支误差度量的功能，比较路径误差 度量，并选择具有最低路径错误度量的路径。 在本发明中，ACS模块可以具有与其动态相关联的两个或更多个序列模型状态，使得在某些时候一个序列模型状态与其相关联，并且在其他时间，另一个序列模型状态与其相关联。 这减少了所需的ACS模块的数量，并且还降低了解调器的路径存储器的大小/复杂性，这些存储器必须存储每个ACS模块的一个路径。 与原始的未导通的维特比解调器相比，可以选择一组序列模型状态来共享ACS模块而没有显着的性能损失。 本发明通过使分离的介质跃迁的预期采样序列可编程化来支持范围广泛的样本模型。 本发明通过允许同时处理多个采样来降低检测器电路相对于采样率运行的速度。 针对特定应用提出了特定样品序列模型的几种降低检测器。 本发明可应用于其它类型的维特比检测器，例如用于卷积码的解码器。

公开(公告)号：US5220295A

公开(公告)日：1993-06-15

申请号：US867978

申请日：1992-04-13

申请人： Neal Glover ,  Peter Murray

发明人： Neal Glover ,  Peter Murray

IPC分类号： H03L7/095 ,  H03L7/10

CPC分类号： H03L7/095 ,  H03L7/10 ,  Y10S331/02

摘要： A Loss of Lock Detector and Re-lock Control function using digital techniques to detect a programmable difference in frequencies over a programmable range. Once Loss of Lock is detected, the Re-lock sequence is initiated and PLLIS, PLLMS & PLLGS are stepped through a programmable sequence. The invention detects the frequency difference by counting down two counters and evaluating the value left in one when the other reaches terminal count using a programmable tolerance of frequency differences before Loss of Lock is declared. The complexity and cost of implementation of the invention is reduced by multiple use of a single down counter. Other features of the invention are disclosed.

摘要翻译： 锁定检测器的丢失和重新锁定控制功能，使用数字技术来检测可编程范围内的可编程差频。 一旦检测到锁定失败，则启动重锁序列，PLLIS，PLLMS和PLLGS通过可编程序列进行步进。 本发明通过对两个计数器进行倒数来检测频率差异，并且当另一个在声明失效之前使用可变容差的频率差达到终端计数时评估剩余的值。 通过多次使用单个向下计数器来减少本发明的实现的复杂性和成本。 公开了本发明的其它特征。

公开(公告)号：US07885255B2

公开(公告)日：2011-02-08

申请号：US12126188

申请日：2008-05-23

申请人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

发明人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

IPC分类号： H04L12/50

摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

公开(公告)号：US07379452B2

公开(公告)日：2008-05-27

申请号：US10028871

申请日：2001-12-21

申请人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

发明人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

IPC分类号： H04L12/50

CPC分类号： G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1258 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B2020/1476 ,  H03M13/31

摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(l,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, error-tolerant sync mark detection, and the ability to recover data when the sync mark is obliterated allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating analog as well as digital functions of the read channel in a single integrated circuit, and embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

摘要翻译： 公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道 。 集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。 这些特性，容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略来最大限度地提高数据恢复的可能性。 公开了包括在单个集成电路中并入模拟量以及读取通道的数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂性的可编程修改维特比检测器的实施例。