公开(公告)号：US20060069839A1

公开(公告)日：2006-03-30

申请号：US10955558

申请日：2004-09-30

申请人： William Moyer ,  Brett Murdock

发明人： William Moyer ,  Brett Murdock

IPC分类号： G06F13/36

CPC分类号： G06F13/368

摘要： A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

公开(公告)号：US20060053256A1

公开(公告)日：2006-03-09

申请号：US10631136

申请日：2004-09-09

申请人： William Moyer ,  Lea Lee ,  Afzal Malik

发明人： William Moyer ,  Lea Lee ,  Afzal Malik

IPC分类号： G06F12/00

CPC分类号： G06F12/0215 ,  Y02D10/13

摘要： In one embodiment, a data processing system (10) includes a first master, storage circuitry (35) coupled to the first master (12) for use by the first master (12), a first control storage circuit (38) which stores a first prefetch limit (60), a prefetch buffer (42), and prefetch circuitry (40) coupled to the first control storage circuit, to the prefetch buffer, and to the storage circuitry. In one embodiment, the prefetch circuitry (40) selectively prefetches a predetermined number of lines from the storage circuitry into the prefetch buffer (42) based on whether or not a prefetch counter, initially set to a value indicated by the first prefetch limit, has expired. In one embodiment, the first prefetch limit may therefore be used to control how many prefetches occur between misses in the prefetch buffer.

摘要翻译： 在一个实施例中，数据处理系统（10）包括第一主机，耦合到第一主机（12）以供第一主机（12）使用的存储电路（35），第一控制存储电路（38） 第一预取限制（60），预取缓冲器（42）和耦合到第一控制存储电路的预取电路（40）到预取缓冲器以及存储电路。 在一个实施例中，预取电路（40）基于是否初始设置为由第一预取限制指示的值的预取计数器是否具有预取数计数器（40）具有预定数量的行从存储电路到预取缓冲器（42） 已过期 在一个实施例中，因此可以使用第一预取限制来控制在预取缓冲器中的未命中之间发生多少个预取。

公开(公告)号：US20050273562A1

公开(公告)日：2005-12-08

申请号：US11197830

申请日：2005-08-05

申请人： William Moyer

发明人： William Moyer

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC分类号： G06F11/3648 ,  G06F12/0888 ,  G06F12/126

摘要： A read allocation indicator (e.g. read allocation signal 30) is provided to storage circuitry (e.g. cache 22) to selectively determine whether read allocation will be performed for the read access. Read allocation may include modification of the information content of the cache (22) and/or modification of the read replacement algorithm state implemented by the read allocation circuitry (70) in cache (22). For certain types of debug operations, it may be very useful to provide a read allocation indicator that ensures that no unwanted modification are made to the storage circuitry during a read access. Yet other types of debug operations may want the storage circuitry to be modified in the standard manner when a read access occurs.

公开(公告)号：US20050198413A1

公开(公告)日：2005-09-08

申请号：US10792591

申请日：2004-03-03

申请人： William Moyer

发明人： William Moyer

IPC分类号： G06F13/00 ,  G06F13/38

CPC分类号： G06F13/385

摘要： Multiple burst memory access handling protocols may be implemented at the hardware level or evaluated and selected during design of the hardware. The appropriate burst protocol may be selectable based on burst characteristics such as burst types and the identity of the current bus master. This allows, for example, the ability for a slave to support multiple error protocols in a multi-master system on a chip (SoC), or to design slaves capable of interfacing with a variety of masters which use different burst handling protocols. Inputs such as a programmable control register or configuration pins or variables may be provided to as part of the slave or slave interface block (e.g., a memory controller) to facilitate the implementation of alternate burst protocols. When a burst request is received from a master, a burst characteristic corresponding to the requested burst is determined and one of a plurality of burst error protocols is selected based on the burst characteristic. The burst request is then processed according to the selected burst error protocol.

摘要翻译： 可以在硬件级实现多个突发存储器访问处理协议，或者在硬件设计期间进行评估和选择。 可以基于诸如突发类型和当前总线主机的标识的突发特性来选择适当的突发协议。 这允许例如从机在芯片上的多主系统（SoC）中支持多个错误协议的能力，或者设计能够与使用不同突发处理协议的各种主机接口的从属设备。 可以将诸如可编程控制寄存器或配置引脚或变量的输入提供给从属或从属接口块（例如，存储器控制器）的一部分，以便于实施替代突发协议。 当从主机接收到突发请求时，确定与所请求的突发相对应的突发特性，并且基于突发特性来选择多个突发错误协议中的一个。 然后根据所选择的突发错误协议来处理突发请求。

公开(公告)号：US20050039039A1

公开(公告)日：2005-02-17

申请号：US10638795

申请日：2003-08-11

申请人： William Moyer ,  Thomas Tkacik

发明人： William Moyer ,  Thomas Tkacik

IPC分类号： G06F9/32 ,  G06F9/455 ,  G06F11/30 ,  G06F12/14 ,  H01L20060101 ,  H03K19/00 ,  H04L9/00 ,  H04L9/32

CPC分类号： G06F11/3648 ,  G06F21/71

摘要： The invention relates to debug circuitry (20) and more particularly to a method and apparatus for providing security for debug circuitry (20). In one embodiment, a plurality of non-volatile elements (38) are used in providing selective disabling and re-enabling of at least a portion of the debug circuitry (20). Authentication may also be used. The present invention may use any debug interface, including standard debug interfaces such as the JTAG debug interface defined by the IEEE.

摘要翻译： 本发明涉及调试电路（20），更具体地说，涉及一种为调试电路（20）提供安全性的方法和装置。 在一个实施例中，使用多个非易失性元件（38）来提供对调试电路（20）的至少一部分的选择性禁用和重新启用。 也可以使用认证。 本发明可以使用任何调试接口，包括诸如由IEEE定义的JTAG调试接口的标准调试接口。

公开(公告)号：US20070226462A1

公开(公告)日：2007-09-27

申请号：US11385463

申请日：2006-03-21

申请人： Jeffrey Scott ,  William Moyer

发明人： Jeffrey Scott ,  William Moyer

IPC分类号： G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/3814 ,  G06F12/0862 ,  G06F2212/6022 ,  Y02D10/13

摘要： A data processor (102) includes a prefetch buffer (112) and a fetch control unit (116). The prefetch buffer (112) has a plurality of lines. The prefetch buffer (112) has a variable maximum depth that defines a number of lines of the plurality of lines that are capable of storing instructions. The fetch control unit (116) is coupled to the prefetch buffer to monitor at least one of the plurality of lines of the prefetch buffer (112) and to adjust the variable maximum depth of the prefetch buffer (112) in response to a state of the data processor (102).

摘要翻译： 数据处理器（102）包括预取缓冲器（112）和获取控制单元（116）。 预取缓冲器（112）具有多条线。 预取缓冲器（112）具有可变的最大深度，其定义能够存储指令的多行的行数。 获取控制单元（116）耦合到预取缓冲器以监视预取缓冲器（112）的多行中的至少一行并且响应于预取缓冲器（112）的状态来调整预取缓冲器（112）的可变最大深度 数据处理器（102）。

公开(公告)号：US20070220354A1

公开(公告)日：2007-09-20

申请号：US11359329

申请日：2006-02-21

申请人： William Moyer

发明人： William Moyer

IPC分类号： G06F11/00

CPC分类号： G06F11/1052

摘要： A device and method for error correction are disclosed. The device includes a memory control module to disable error processing for a memory location depending on the state of a status indicator. The status indicator can be set so that error processing is disabled when valid error correction and detection information for the memory location is not available, such as after a reset or power-on event. In addition, the memory control module can promote partial write requests to full write requests when error processing is disabled to ensure that valid error detection and correction data is calculated for the memory location. By disabling error processing until valid error detection and correction information is available, the number of unnecessary or invalid error processing operations is reduced, thereby conserving device resources.

摘要翻译： 公开了一种用于纠错的装置和方法。 该设备包括一个存储器控制模块，用于根据状态指示器的状态来禁止存储器位置的错误处理。 可以设置状态指示器，使得当有效的纠错和存储器位置的检测信息不可用时（例如在复位或开机事件之后），禁用错误处理。 此外，当禁用错误处理时，存储器控制模块可以促进对完全写入请求的部分写入请求，以确保为存储器位置计算有效的错误检测和校正数据。 通过禁用错误处理，直到有效的错误检测和校正信息可用，减少了不必要或无效的错误处理操作的数量，从而节省了设备资源。

公开(公告)号：US20070198804A1

公开(公告)日：2007-08-23

申请号：US11360926

申请日：2006-02-23

申请人： William Moyer

发明人： William Moyer

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F12/0292

摘要： In a data processing system a processor including processing logic performs data processing. An address translator that is coupled to the processing logic performs address translation and a method thereof. The address translator receives a logical address and converts the logical address to both a physical address and one or more address attributes. Bypass circuitry that is coupled to the address translator selectively provides the logical address as a translated address of the logical address which was received. In order to speed up the memory address translation, the logical address is selectively provided as the translated address prior to providing the one or more address attributes associated with the logical address.

摘要翻译： 在数据处理系统中，包括处理逻辑的处理器执行数据处理。 耦合到处理逻辑的地址转换器执行地址转换及其方法。 地址转换器接收逻辑地址并将逻辑地址转换为物理地址和一个或多个地址属性。 耦合到地址转换器的旁路电路选择性地将逻辑地址提供为所接收的逻辑地址的翻译地址。 为了加速存储器地址转换，在提供与逻辑地址相关联的一个或多个地址属性之前，逻辑地址被选择性地提供为转换的地址。

公开(公告)号：US20060282621A1

公开(公告)日：2006-12-14

申请号：US11149670

申请日：2005-06-10

申请人： William Moyer

发明人： William Moyer

IPC分类号： G06F13/28

CPC分类号： G06F12/0864 ,  G06F9/3802 ,  G06F9/3814 ,  G06F12/0882 ,  G06F2212/1028 ,  Y02D10/13

摘要： Techniques for accessing a unified cache to obtain instruction information are provided. One exemplary technique includes accessing, during a first instruction access, a first cache line of a first way of a unified cache having a plurality of ways to obtain instruction information associated with a first instruction, enabling the first way and disabling one or more of the remaining ways of the unified cache in response to a determination that the first cache line comprises instruction information associated with a second instruction, and accessing, during a second instruction access, the first cache line of the first way to obtain instruction information associated with the second instruction.

摘要翻译： 提供了访问统一缓存以获取指令信息的技术。 一种示例性技术包括在第一指令访问期间访问具有多种方式的统一高速缓存的第一方式的第一高速缓存行，以获得与第一指令相关联的指令信息，从而实现第一方式并禁用一个或多个 响应于确定第一高速缓存行包括与第二指令相关联的指令信息以及在第二指令访问期间访问第一方式的第一高速缓存行以获得与第二指令相关联的指令信息的统一缓存的剩余方式 指令。

公开(公告)号：US20060155974A1

公开(公告)日：2006-07-13

申请号：US11031826

申请日：2005-01-07

申请人： William Moyer ,  Peter Wilson

发明人： William Moyer ,  Peter Wilson

IPC分类号： G06F9/44

CPC分类号： G06F9/30181 ,  G06F9/30196 ,  G06F9/32

摘要： If a data processing system (10) implements more than one instruction set within a single processor (12), then program portions encoded using a first instruction set will need to be able to call program portions encoded using a second instruction set. This switching between instruction sets requires that the processor (12) be informed when instruction execution is switching between the plurality of instruction sets. A solution was needed that would allow program portions to freely intermix their usage of different instruction sets with no prior knowledge by the software programmer as to which instruction set is used for which program portion. In one embodiment, instruction address attribute (106) in address mapping circuitry (32) may be used to inform instruction decode unit (46) of processor (12) when instruction execution is switching between the plurality of instruction sets.

摘要翻译： 如果数据处理系统（10）在单个处理器（12）内实现多于一个的指令集，则使用第一指令集编码的程序部分将需要能够调用使用第二指令集编码的程序部分。 指令集之间的切换要求当指令执行在多个指令集之间切换时通知处理器（12）。 需要一种解决方案，这将允许程序部分自由地混合其使用不同的指令集，而无需软件程序员事先知道哪个指令集用于哪个程序部分。 在一个实施例中，当指令执行在多个指令集之间切换时，地址映射电路（32）中的指令地址属性（106）可用于通知处理器（12）的指令解码单元（46）。