公开(公告)号：US20070266217A1

公开(公告)日：2007-11-15

申请号：US11382900

申请日：2006-05-11

申请人： William Moyer ,  Jeffrey Scott

发明人： William Moyer ,  Jeffrey Scott

IPC分类号： G06F12/00

CPC分类号： G06F12/0804 ,  G06F9/30043 ,  G06F9/30181 ,  G06F9/3824 ,  G06F12/0888

摘要： A processing system and method performs allocation of memory cache lines in response to a cache write miss. A processor receives a plurality of data processing instructions. A first store instruction for storing data in a system memory at a predetermined address is decoded by decoding a first specifier within the first store instruction. The first specifier determines an allocation policy for the first store instruction wherein the allocation policy determines whether to store data within the cache when the predetermined address is not within the cache. Additional store instructions are decoded. For example, a second specifier determines an allocation policy for a second store instruction. The specifier in each of the store instructions may be implemented in various forms to provide a policy indicator for each store instruction. No allocation policy may also be established on a per-access basis.

摘要翻译： 处理系统和方法响应于高速缓存写入未命中而执行存储器高速缓存行的分配。 处理器接收多个数据处理指令。 通过对第一存储指令内的第一说明符进行解码来解码用于将数据存储在预定地址的系统存储器中的第一存储指令。 第一说明符确定第一存储指令的分配策略，其中当预定地址不在高速缓存内时，分配策略确定是否在高速缓存中存储数据。 额外的存储指令被解码。 例如，第二说明符确定第二存储指令的分配策略。 每个存储指令中的说明符可以以各种形式实现，以为每个存储指令提供策略指示符。 也可以在每个访问的基础上建立分配策略。

公开(公告)号：US20070226462A1

公开(公告)日：2007-09-27

申请号：US11385463

申请日：2006-03-21

申请人： Jeffrey Scott ,  William Moyer

发明人： Jeffrey Scott ,  William Moyer

IPC分类号： G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/3814 ,  G06F12/0862 ,  G06F2212/6022 ,  Y02D10/13

摘要： A data processor (102) includes a prefetch buffer (112) and a fetch control unit (116). The prefetch buffer (112) has a plurality of lines. The prefetch buffer (112) has a variable maximum depth that defines a number of lines of the plurality of lines that are capable of storing instructions. The fetch control unit (116) is coupled to the prefetch buffer to monitor at least one of the plurality of lines of the prefetch buffer (112) and to adjust the variable maximum depth of the prefetch buffer (112) in response to a state of the data processor (102).

摘要翻译： 数据处理器（102）包括预取缓冲器（112）和获取控制单元（116）。 预取缓冲器（112）具有多条线。 预取缓冲器（112）具有可变的最大深度，其定义能够存储指令的多行的行数。 获取控制单元（116）耦合到预取缓冲器以监视预取缓冲器（112）的多行中的至少一行并且响应于预取缓冲器（112）的状态来调整预取缓冲器（112）的可变最大深度 数据处理器（102）。

公开(公告)号：US20060095723A1

公开(公告)日：2006-05-04

申请号：US11297682

申请日：2005-12-07

申请人： William Moyer ,  John Arends ,  Jeffrey Scott

发明人： William Moyer ,  John Arends ,  Jeffrey Scott

IPC分类号： G06F15/00

CPC分类号： G06F9/3881

摘要： A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

摘要翻译： 支持多个协处理器（14,16）的协处理器（14）接口的处理器（12）利用编译器可产生的软件类型函数调用和返回，指令执行以及可变加载和存储接口指令。 数据在双向共享总线（28）上的处理器（12）和协处理器（14）之间隐含地通过寄存器窥探和广播来移动，或通过功能调用和返回以及可变负载和存储接口指令明确地移动。 加载和存储接口指令允许选择性存储器地址预增量。 双向总线（28）可以在每个时钟周期两方面潜在地驱动。 接口分离接口指令解码和执行。 通过在执行信号被断言之前否定解码信号来指示解码的指令丢弃来提供流水线操作。

公开(公告)号：US20050132173A1

公开(公告)日：2005-06-16

申请号：US10736393

申请日：2003-12-15

申请人： William Moyer ,  Jeffrey Scott

发明人： William Moyer ,  Jeffrey Scott

IPC分类号： G06F9/00 ,  G06F9/38 ,  G06F15/00

CPC分类号： G06F9/382 ,  G06F9/3806

摘要： A method (200) and apparatus (100) for allocating entries in a branch target buffer (BTB) (144) in a pipelined data processing system includes: sequentially fetching instructions; determining that one of the instructions is a branch instruction (210, 215, 220); decoding the branch instruction to determine a branch target address; determining if the branch target address can be obtained without causing a stall condition in the pipelined data processing system; and selectively allocating an entry of the BTB (144) based on the determination. In one embodiment, an entry of the BTB (144) is allocated if the branch instruction is not loaded into a predetermined slot (S1) of a prefetch buffer (102) and no other stall condition will occur. The method (200) and apparatus (100) combine the advantages of using a BTB (144) and branch lookahead to reduce stall conditions in the data processing system.

摘要翻译： 一种用于在流水线数据处理系统中分配目标缓冲器（BTB）（144）中的条目的方法（200）和装置（100）包括：顺序取指令; 确定所述指令之一是分支指令（210,215,220）; 解码分支指令以确定分支目标地址; 确定是否可以获得分支目标地址而不导致流水线数据处理系统中的停顿状态; 以及基于所述确定来选择性地分配所述BTB（144）的条目。 在一个实施例中，如果分支指令未被加载到预取缓冲器（102）的预定时隙（S1）中并且不会发生其它失速条件，则分配BTB（144）的条目。 方法（200）和装置（100）组合使用BTB（144）和分支前视的优点来减少数据处理系统中的失速状况。

公开(公告)号：US08780728B1

公开(公告)日：2014-07-15

申请号：US12341790

申请日：2008-12-22

申请人： Michael Woodley ,  Jeffrey Scott ,  Jeffrey Goff

发明人： Michael Woodley ,  Jeffrey Scott ,  Jeffrey Goff

IPC分类号： H04L12/26

CPC分类号： H04W24/06 ,  H04L5/0007 ,  H04L5/003 ,  H04L5/0037 ,  H04L5/0046 ,  H04L5/0062 ,  H04L5/0091 ,  H04L5/0094 ,  H04W72/044 ,  H04W88/02

摘要： A radio frequency radio (RF) transceiver that defines scheduling logic for generating transmission schedules for orthogonal frequency-division multiple access (OFDMA) RF transmissions from the RF transceiver, wherein the scheduling logic specifies at least one of a modulation type, a code rate, a sub-channel, and a sub-carrier for a plurality of symbols to be transmitted in a communication signal sub-frame. A processor generates outgoing data bits and outgoing test data bits for transmission from the RF transceiver as OFDMA transmission signals and OFDMA test data transmission signals, respectively, according to the transmission schedules to create loading within at least a portion of a cellular service area that corresponds with a test-loading value. The amount of the additional required loading is the difference between the test-loading value and an actual loading value.

摘要翻译： 一种射频收发器，其定义用于从所述RF收发器生成用于正交频分多址（OFDMA）RF传输的传输调度的调度逻辑，其中所述调度逻辑指定调制类型，码率， 子信道和用于要在通信信号子帧中发送的多个符号的子载波。 处理器根据传输时间表分别产生输出数据位和输出测试数据位，以从RF收发器传输作为OFDMA传输信号和OFDMA测试数据传输信号，以在对应的蜂窝服务区域的至少一部分内创建负载 具有测试加载值。 额外的所需负载量是试验载荷值和实际载荷值之间的差值。

公开(公告)号：US08278027B2

公开(公告)日：2012-10-02

申请号：US13188377

申请日：2011-07-21

申请人： Jeffrey Scott ,  Michael Zani ,  Mark Bennahmias ,  Mark Mayse

发明人： Jeffrey Scott ,  Michael Zani ,  Mark Bennahmias ,  Mark Mayse

IPC分类号： G03C5/00

CPC分类号： H01J37/3174 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/3177 ,  H01L21/0331 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26533 ,  H01L21/28123 ,  H01L21/30621 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S430/143

摘要： A manufacturing process technology creates a pattern on a first layer using a focused ion beam process. The pattern is transferred to a second layer, which may act as a traditional etch stop layer. The pattern can be formed on the second layer without irradiation by light through a reticle and without wet chemical developing, thereby enabling conformal coverage and very fine critical feature control. Both dark field patterns and light field patterns are disclosed, which may enable reduced or minimal exposure by the focused ion beam.

摘要翻译： 制造工艺技术使用聚焦离子束工艺在第一层上创建图案。 该图案被转移到第二层，其可以用作传统的蚀刻停止层。 图案可以形成在第二层上，而不用光线通过掩模版而没有湿化学显影，从而实现适形覆盖和非常精细的关键特征控制。 公开了两种暗场图案和光场图案，其可以实现聚焦离子束的减少或最小曝光。

公开(公告)号：US20120028464A1

公开(公告)日：2012-02-02

申请号：US13188377

申请日：2011-07-21

申请人： Jeffrey Scott ,  Michael Zani ,  Mark Bennahmias ,  Mark Mayse

发明人： Jeffrey Scott ,  Michael Zani ,  Mark Bennahmias ,  Mark Mayse

IPC分类号： H01L21/44

CPC分类号： H01J37/3174 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/3177 ,  H01L21/0331 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26533 ,  H01L21/28123 ,  H01L21/30621 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S430/143

摘要： A manufacturing process technology creates a pattern on a first layer using a focused ion beam process. The pattern is transferred to a second layer, which may act as a traditional etch stop layer. The pattern can be formed on the second layer without irradiation by light through a reticle and without wet chemical developing, thereby enabling conformal coverage and very fine critical feature control. Both dark field patterns and light field patterns are disclosed, which may enable reduced or minimal exposure by the focused ion beam.

摘要翻译： 制造工艺技术使用聚焦离子束工艺在第一层上创建图案。 该图案被转移到第二层，其可以用作传统的蚀刻停止层。 图案可以形成在第二层上，而不用光线通过掩模版而没有湿化学显影，从而实现适形覆盖和非常精细的关键特征控制。 公开了两种暗场图案和光场图案，其可以实现聚焦离子束的减少或最小的曝光。

公开(公告)号：US20070054629A1

公开(公告)日：2007-03-08

申请号：US10730404

申请日：2003-12-08

申请人： James Maligeorgos ,  Augusto Marques ,  Lysander Lim ,  G. Tuttle ,  Aslamali Rafi ,  Tod Paulus ,  Gregory Uehara ,  Jeffrey Scott ,  Richard Behrens ,  Donald Kerth ,  G. Vishakhadatta ,  Vishnu Srinivasan ,  Caiyi Wang

发明人： James Maligeorgos ,  Augusto Marques ,  Lysander Lim ,  G. Tuttle ,  Aslamali Rafi ,  Tod Paulus ,  Gregory Uehara ,  Jeffrey Scott ,  Richard Behrens ,  Donald Kerth ,  G. Vishakhadatta ,  Vishnu Srinivasan ,  Caiyi Wang

IPC分类号： H04B1/38

CPC分类号： H04B1/30 ,  H03J2200/10 ,  H04L27/0002

摘要： Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry. Automatic frequency control (AFC) circuitry may be integrated with other components of RF circuitry and may generate frequency control signals for the frequency modification circuitry based on, for example, a signal received from a temperature sensor. Digital-to-analog converter (DAC) circuitry may be integrated with other components of RF circuitry to enable all-digital frequency control communications from baseband processor circuitry to RF circuitry.

摘要翻译： 包括生成具有可变频率的参考信号的晶体振荡器电路的收发器电路和频率修改电路的射频（RF）设备的组件可以以各种方式被划分，例如作为一个或多个单独的集成电路。 频率修改电路可以被实现为包括数字控制的晶体振荡器（“DCXO”）电路和晶体的晶体振荡器电路的一部分。 频率修改电路可以包括至少一个可变电容器件，并且可以用于产生具有可调频率的参考信号。 可调参考信号可以被提供给RF装置的其他部件，和/或RF装置可以被配置为向基带处理器电路提供可调参考信号。 自动频率控制（AFC）电路可以与RF电路的其它组件集成，并且可以基于例如从温度传感器接收的信号来生成用于频率修改电路的频率控制信号。 数模转换器（DAC）电路可以与RF电路的其他部件集成，以实现从基带处理器电路到RF电路的全数字频率控制通信。

公开(公告)号：US20100196864A1

公开(公告)日：2010-08-05

申请号：US12798842

申请日：2010-04-13

申请人： Charles Q. Lee ,  Amy H. Lee ,  Jeffrey Scott

发明人： Charles Q. Lee ,  Amy H. Lee ,  Jeffrey Scott

IPC分类号： G09B23/30

CPC分类号： G09B23/28 ,  A61C19/042 ,  G09B23/283

摘要： A dental training aid and method which assists a student in learning how to determine the position of a root canal apex, repair of dental decay, and how to perform crown and bridge procedures. In certain embodiments, modular inserts are utilized that include structure thereon for performing root canal procedures, repair of dental decay procedures, crown and bridge procedures or other procedures. The inserts can be assembled and configured to all provide practice on the same procedure or on different procedures and can be exchanged for other inserts once they are no longer reusable or because the user wants to train on a different procedure.

公开(公告)号：US20070101851A1

公开(公告)日：2007-05-10

申请号：US11593209

申请日：2006-11-06

申请人： Scott McIntosh ,  John Wate ,  Jeffrey Scott

发明人： Scott McIntosh ,  John Wate ,  Jeffrey Scott

IPC分类号： B23D55/02 ,  B26D7/26 ,  B27B13/02

CPC分类号： B23D53/12 ,  B23D53/006 ,  Y10T29/49826 ,  Y10T29/49959 ,  Y10T83/04 ,  Y10T83/6995 ,  Y10T83/7025 ,  Y10T83/707 ,  Y10T83/8763 ,  Y10T83/95

摘要： A method and apparatus for converting a portable band saw to an upright stationary table band saw includes a stand having a base, at least one vertically extending side wall, and a top. A work piece support surface can include an opening through which one run of a closed loop saw blade of the portable band saw can pass when the portable band saw is mounted in a supporting relationship with respect to the stand. A switch mounted on the stand operates the portable band saw independent of the finger trigger on the handle. The on/off switch is connected to a plug engaged by the portable band saw when mounted in the stand. The plug is engagable within a socket of the band saw and is electrically connected to bypass the finger trigger of the portable band saw and to create a circuit through the on/off switch.

摘要翻译： 用于将便携式带锯转换成立式固定台带锯的方法和装置包括具有底座，至少一个垂直延伸的侧壁和顶部的支架。 工件支撑表面可以包括当便携式带锯相对于支架以支撑关系安装时便携式带锯的闭环锯片的一个行程通过的开口。 安装在支架上的开关可独立于手柄上的手指触发器操作便携式带锯。 当安装在支架上时，开/关开关连接到由便携式带锯接合的插头。 插头可以在带锯的插座内接合并且被电连接以绕过便携式带锯的手指触发器并且通过开/关开关创建电路。