-
公开(公告)号：US06198348B1
公开(公告)日：2001-03-06
申请号：US09346032
申请日：1999-07-01
IPC分类号： H03F345
CPC分类号： H03F1/48 , H03F3/4508 , H03F2200/36
摘要： A differential circuit (200) provides for reverse isolation between input and output ports (202, 204). The differential circuit has amplification circuitry that includes active transistors (221, 222) and reverse isolation circuitry that employ transistors (223,224) having similar manufacturing and processing characteristics to couple the input and output ports (202, 204).
摘要翻译： 差分电路（200）提供输入和输出端口（202,204）之间的反向隔离。 差分电路具有放大电路，其包括有源晶体管（221,222）和反向隔离电路，其采用具有相似制造和处理特性的晶体管（223,224）来耦合输入和输出端口（202,204）。
-
32.发明授权Method and apparatus for reducing even order distortion in differential circuits 有权降低差分电路中偶数阶失真的方法和装置
公开(公告)号：US6118322A
公开(公告)日：2000-09-12
申请号：US185263
申请日：1998-11-03
摘要： An apparatus (100) includes a differential processing circuit (135) responsive to an input signal with first and second signal components, and a signal imbalance suppressor (130) that preprocesses the input signal, prior to input to the differential processing circuit, to remove amplitude and/or phase imbalances that exist between the first and second signal components, in order to reduce even order distortion generation within the differential processing circuit.
摘要翻译： 一种设备（100）包括响应于具有第一和第二信号分量的输入信号的差分处理电路（135），以及在输入到差分处理电路之前预处理输入信号的信号不平衡抑制器（130）以去除 存在于第一和第二信号分量之间的幅度和/或相位不平衡，以便减少差分处理电路内的偶数阶失真产生。
-
公开(公告)号：US5648766A
公开(公告)日：1997-07-15
申请号：US352302
申请日：1994-12-08
申请人： Robert E. Stengel , David L. Muri
发明人： Robert E. Stengel , David L. Muri
CPC分类号： G05F1/46
摘要： An electronic device (100) includes a regulator (102) for generating an operating voltage. The device (100) also includes at least one component (110) using the operating voltage and requiring a minimum input voltage for proper operation. The device (100) further includes a sensor (115) for sensing the minimum input voltage of the component (110) to produce a minimum operating voltage. Also included in the device (100) is a feedback circuit (116), responsive to the sensor (115), for feeding the minimum operating voltage to the regulator (102) whereby the regulator (102) alters the output voltage to the level of the minimum operating voltage.
摘要翻译： 电子设备（100）包括用于产生工作电压的调节器（102）。 设备（100）还包括使用工作电压的至少一个部件（110），并且需要最小输入电压以进行适当的操作。 装置（100）还包括用于感测部件（110）的最小输入电压以产生最小工作电压的传感器（115）。 设备（100）中还包括响应于传感器（115）的反馈电路（116），用于将最小工作电压馈送到调节器（102），由此调节器（102）将输出电压改变为 最小工作电压。
-
34.发明授权
公开(公告)号：US5574353A
公开(公告)日：1996-11-12
申请号：US414816
申请日：1995-03-31
申请人： Lijun Bai , Ke K. Lian , Robert E. Stengel
发明人： Lijun Bai , Ke K. Lian , Robert E. Stengel
CPC分类号： H01M4/38 , H01M10/44 , H01M2300/0014
摘要： An electrochemical charge storage device (20) having a voltage discharge profile which is constant for a substantial period of the discharge cycle, which then drops off sharply to full discharge, in a manner more often associated with a battery discharge profile. The electrochemical charge storage device is further characterized by a discharge rate in excess of at least 100 C., and as much as 7000 C. Accordingly, the electrochemical charge storage device is characterized by a battery discharge voltage profile which occurs at substantially capacitor discharge rates.
摘要翻译： 电化学电荷存储装置（20）具有电压放电曲线，该电压放电曲线在放电周期的实际周期内是恒定的，然后电压放电曲线以与电池放电曲线更经常相关的方式急剧下降至全放电。 电化学电荷存储装置的特征还在于放电速率超过至少100℃，高达7000℃。因此，电化学电荷存储装置的特征在于电池放电电压曲线，其基本上以电容器放电率 。
-
公开(公告)号：US5218284A
公开(公告)日：1993-06-08
申请号：US636480
申请日：1990-12-31
申请人： Arthur G. Burns , Robert E. Stengel
发明人： Arthur G. Burns , Robert E. Stengel
CPC分类号： H02J7/34 , H02J9/061 , H02J7/0011 , Y10S320/24
摘要： A rechargeable battery (10) comprises at least one cell (7) having a positive and a negative terminal. Switching regulation circuitry (9) coupled to the cell (7) is selectively used for regulating the battery output (28) and for regulating the charging (12) of the battery.
摘要翻译： 可再充电电池（10）包括至少一个具有正极和负极端子的电池（7）。 耦合到电池（7）的开关调节电路（9）被选择性地用于调节电池输出（28）并用于调节电池的充电（12）。
-
36.发明授权
公开(公告)号：US5204970A
公开(公告)日：1993-04-20
申请号：US648809
申请日：1991-01-31
CPC分类号： H04W52/146 , H04W52/245 , H04W52/248
摘要： A method for adjusting the transmitter power of a subscriber unit includes the steps of determining noise characteristic of a receiver site, measuring strength of a signal received from the subscriber, determining a power adjust value based on the noise characteristic and the received signal strength. The transmit power of the subscriber unit is adjusted according to the power adjust value.
摘要翻译： 一种用于调整用户单元的发射机功率的方法包括以下步骤：确定接收站点的噪声特性，测量从用户接收的信号的强度，基于噪声特性和接收信号强度确定功率调整值。 用户单元的发射功率根据功率调整值进行调整。
-
37.发明授权Method and apparatus for fast frequency locking in a closed loop based frequency synthesizer 有权用于在基于闭环的频率合成器中快速锁定的方法和装置公开(公告)号：US08427205B1
公开(公告)日：2013-04-23
申请号：US13328240
申请日：2011-12-16
CPC分类号： H03L7/0814
摘要： A synthesizer comprises a first processing unit that receives digital information relating to a required final frequency of the synthesizer and determines a primary frequency value and a corresponding frequency multiplier mode. A primary synthesizer receives the primary frequency value and an external reference frequency signal to generate a signal of the primary frequency. The synthesizer further comprises a second processing unit that receives the primary frequency value, determines a pre-charge voltage value corresponding to the primary frequency value, and transmits the pre-charge voltage value to a delay locked loop in response to a change in the primary frequency value. The delay locked loop receives the signal of primary frequency and the pre-charge value. The DLL is pre-charged to the pre-charge voltage value for a predetermined time, by opening and closing the delay locked loop to obtain fast locking of the synthesizer.
摘要翻译： 合成器包括第一处理单元，其接收与合成器的所需最终频率有关的数字信息，并确定主频率值和相应的倍频器模式。 主合成器接收主要频率值和外部参考频率信号以产生主要频率的信号。 合成器还包括接收主频率值的第二处理单元，确定对应于主频率值的预充电电压值，并响应于主频率的变化将预充电电压值发送到延迟锁定回路 频率值。 延迟锁定环接收主频率和预充电值的信号。 通过打开和关闭延迟锁定环以获得合成器的快速锁定，将DLL预充电到预充电电压值预定时间。
-
公开(公告)号：US07869769B2
公开(公告)日：2011-01-11
申请号：US11946072
申请日：2007-11-28
IPC分类号： H04B1/40
CPC分类号： H03L7/16 , H03K5/15013 , H03L7/07 , H03L7/0812 , H03L7/087
摘要： A frequency generator (100) takes a signal source (clock or carrier) (101) and generates a edge encoded direct digital modulated differential output signal (110). The differential signal (110) is applied to a frequency extension quadrature generator (FEQG) (112). The FEQG (112) includes a fractional differential wavelength delay locked loop (DLL) (280) and a frequency multiplier (240). The DLL (280) generates a control voltage (214) with which to control delays of the edge encoded modulation signal (110). A frequency extended quadrature function is applied to the periodic steady state input signal with edge encoded modulation (110), to provide the output signal set 113.
摘要翻译： 频率发生器（100）接收信号源（时钟或载波）（101）并产生边缘编码直接数字调制差分输出信号（110）。 差分信号（110）被施加到频率扩展正交发生器（FEQG）（112）。 FEQG（112）包括分数差分波长延迟锁定环（DLL）（280）和倍频器（240）。 DLL（280）产生用于控制边缘编码调制信号（110）的延迟的控制电压（214）。 频率扩展正交函数被施加到具有边缘编码调制（110）的周期性稳态输入信号，以提供输出信号组113。
-
公开(公告)号：US20090137211A1
公开(公告)日：2009-05-28
申请号：US11946072
申请日：2007-11-28
CPC分类号： H03L7/16 , H03K5/15013 , H03L7/07 , H03L7/0812 , H03L7/087
摘要： A frequency generator (100) takes a signal source (clock or carrier) (101) and generates a edge encoded direct digital modulated differential output signal (110). The differential signal (110) is applied to a frequency extension quadrature generator (FEQG) (112). The FEQG (112) includes a fractional differential wavelength delay locked loop (DLL) (280) and a frequency multiplier (240). The DLL (280) generates a control voltage (214) with which to control delays of the edge encoded modulation signal (110). A frequency extended quadrature function is applied to the periodic steady state input signal with edge encoded modulation (110), to provide the output signal set 113.
摘要翻译： 频率发生器（100）接收信号源（时钟或载波）（101）并产生边缘编码直接数字调制差分输出信号（110）。 差分信号（110）被施加到频率扩展正交发生器（FEQG）（112）。 FEQG（112）包括分数差分波长延迟锁定环（DLL）（280）和倍频器（240）。 DLL（280）产生用于控制边缘编码调制信号（110）的延迟的控制电压（214）。 频率扩展正交函数被施加到具有边缘编码调制（110）的周期性稳态输入信号，以提供输出信号组113。
-
公开(公告)号：US06998928B2
公开(公告)日：2006-02-14
申请号：US10430099
申请日：2003-05-06
申请人： Robert E. Stengel , Wen Yu
发明人： Robert E. Stengel , Wen Yu
IPC分类号： H03K7/08
CPC分类号： H03L7/0812 , H03K5/131 , H03K5/133 , H03K7/08 , H03L7/0891
摘要： A digital technique for pulse width modulation (PWM) utilizes a tapped delay line 304 receiving a reference clock and generating a plurality of time delayed reference clock transitions having finer time resolution than the reference clock signal. A multiplexer 120 receives the plurality of time delayed reference clock transitions as an input thereto and producing an output when one of the plurality of time delayed reference clock transitions is addressed. An accumulator circuit 524 generates control timing signals associated with the input signal sampling rate Fsample that are used to select outputs from the delay line 304 representing a pulse width modulated output signal.
摘要翻译： 用于脉冲宽度调制（PWM）的数字技术利用抽头延迟线304接收参考时钟并产生具有比参考时钟信号更精细的时间分辨率的多个时间延迟的参考时钟转变。 多路复用器120接收多个时间延迟的参考时钟转换作为其输入，并且在多个时间延迟的参考时钟转换中的一个被寻址时产生输出。 累加器电路524产生与用于选择来自表示脉冲宽度调制输出信号的延迟线304的输出的输入信号采样率F SUB样本相关联的控制定时信号。
-
-
-
-
-
-
-
-
-
搜索结果
82 条记录 (耗时 0.021 秒)
