Method and apparatus for extracting parameters for an electrical structure
    1.
    发明授权
    Method and apparatus for extracting parameters for an electrical structure 有权
    用于提取电气结构参数的方法和装置

    公开(公告)号:US06539344B1

    公开(公告)日:2003-03-25

    申请号:US09553814

    申请日:2000-04-21

    IPC分类号: G06F760

    CPC分类号: G06F17/5036

    摘要: A parameter extraction technique for an electrical structure is based on a definition of network parameters that isolates pure mode responses of the electrical structure, and that makes mode conversion responses of the electrical structure negligible. A set of network parameters is obtained that represents pure mode responses for the electrical structure (410). These network parameters are processed to obtain model parameters that characterize each pure mode response (422, 424, 426, 428, 432, 434, 436, 438). Preferably, the mode specific parameters to combined to obtain mode independent parameters, such as coupling factor, propagation constant, and characteristic impedance values (440, 450).

    摘要翻译: 用于电气结构的参数提取技术基于隔离电气结构的纯模式响应的网络参数的定义,并且使得电气结构的模式转换响应可忽略不计。 获得代表电结构(410)的纯模式响应的一组网络参数。 处理这些网络参数以获得表征每个纯模式响应(422,424,426,428,432,434,436,438)的模型参数。 优选地,组合的模式特定参数以获得模式无关参数,例如耦合因子,传播常数和特征阻抗值(440,450)。

    Variable impedance circuit providing reduced distortion
    3.
    发明授权
    Variable impedance circuit providing reduced distortion 失效
    可变阻抗电路提供减小的失真

    公开(公告)号:US5379008A

    公开(公告)日:1995-01-03

    申请号:US25458

    申请日:1993-03-03

    IPC分类号: H03H7/06 H03H7/00 H03H5/12

    CPC分类号: H03H7/06

    摘要: An electronic circuit (300) includes first (302) and second (304) variable impedance devices coupled together. The first (302) and second (304) variable impedance devices are designed such that each exhibits a transfer function which is substantially inverse with respect to the other about the operating point of the electronic circuit. This provides for an electronic circuit which exhibits very low distortion characteristics. Circuits such as tunable filters, voltage-controlled oscillators (VCOs), receivers, etc. will benefit from using an electronic circuit (300) which exhibits such low distortion characteristics.

    摘要翻译: 电子电路(300)包括耦合在一起的第一(302)和第二(304)可变阻抗器件。 第一(302)和第二(304)可变阻抗装置被设计成使得每个展现出相对于另一个绕电子电路的工作点基本上相反的传递函数。 这提供了具有非常低失真特性的电子电路。 诸如可调谐滤波器,压控振荡器(VCO),接收器等的电路将受益于使用具有这种低失真特性的电子电路(300)。

    Cascaded delay locked loop circuit
    4.
    发明授权
    Cascaded delay locked loop circuit 有权
    级联延迟锁定环路

    公开(公告)号:US07154978B2

    公开(公告)日:2006-12-26

    申请号:US10000914

    申请日:2001-11-02

    IPC分类号: H03D3/24

    摘要: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 . . . 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 . . . 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.

    摘要翻译: 在几个实施例中,延迟锁定环频率合成器使用主延迟线元件(24)和一个或多个辅助延迟元件(162 ... 164,270,310)。 在一个实施例中,主延迟线(24)用于粗略地选择频率输出,而使用无源或有源的辅助延迟元件(162 ... 164,270,310)来增加初级 延迟线(24)。 在被动实施例中,通过从主延迟线(24)的输出抽头中选择分量作为被动次级延迟元件(310)的驱动信号来提供粗调和选择输出,可以进行粗略和精细的频率选择 从第二延迟元件(310)提供精细选择。

    Differential circuit with reverse isolation
    5.
    发明授权
    Differential circuit with reverse isolation 失效
    差分电路具有反向隔离

    公开(公告)号:US06198348B1

    公开(公告)日:2001-03-06

    申请号:US09346032

    申请日:1999-07-01

    IPC分类号: H03F345

    摘要: A differential circuit (200) provides for reverse isolation between input and output ports (202, 204). The differential circuit has amplification circuitry that includes active transistors (221, 222) and reverse isolation circuitry that employ transistors (223,224) having similar manufacturing and processing characteristics to couple the input and output ports (202, 204).

    摘要翻译: 差分电路(200)提供输入和输出端口(202,204)之间的反向隔离。 差分电路具有放大电路,其包括有源晶体管(221,222)和反向隔离电路,其采用具有相似制造和处理特性的晶体管(223,224)来耦合输入和输出端口(202,204)。

    Method and apparatus for reducing even order distortion in differential
circuits
    6.
    发明授权
    Method and apparatus for reducing even order distortion in differential circuits 有权
    降低差分电路中偶数阶失真的方法和装置

    公开(公告)号:US6118322A

    公开(公告)日:2000-09-12

    申请号:US185263

    申请日:1998-11-03

    CPC分类号: H03D3/009 H03F1/32

    摘要: An apparatus (100) includes a differential processing circuit (135) responsive to an input signal with first and second signal components, and a signal imbalance suppressor (130) that preprocesses the input signal, prior to input to the differential processing circuit, to remove amplitude and/or phase imbalances that exist between the first and second signal components, in order to reduce even order distortion generation within the differential processing circuit.

    摘要翻译: 一种设备(100)包括响应于具有第一和第二信号分量的输入信号的差分处理电路(135),以及在输入到差分处理电路之前预处理输入信号的信号不平衡抑制器(130)以去除 存在于第一和第二信号分量之间的幅度和/或相位不平衡,以便减少差分处理电路内的偶数阶失真产生。

    Apparatus and method for generating accurate quadrature over a frequency range
    7.
    发明授权
    Apparatus and method for generating accurate quadrature over a frequency range 有权
    用于在频率范围内产生精确正交的装置和方法

    公开(公告)号:US06222405B1

    公开(公告)日:2001-04-24

    申请号:US09507722

    申请日:2000-02-22

    IPC分类号: H03H1116

    CPC分类号: H03H11/16

    摘要: The invention produces an accurate quadrature relationship for a range of frequencies using passive components in the primary quadrature splitting circuits. A reference oscillator (202) generates a reference signal which is fed to a conventional passive quadrature splitter circuit (204). However, since the reference circuit provides signals over a range of frequencies, the output signals of the passive quadrature splitter may not have an accurate quadrature relationship. The output signals of the passive quadrature splitter are then equalized in magnitude, and the sum and difference of the signals are produced, which will be in an accurate quadrature relationship.

    摘要翻译: 本发明使用主要正交分离电路中的无源部件在一定频率范围内产生精确的正交关系。 参考振荡器(202)产生馈送到常规无源正交分离器电路(204)的参考信号。 然而,由于参考电路在一定范围的频率上提供信号,所以无源正交分离器的输出信号可能不具有精确的正交关系。 然后,无源正交分波器的输出信号在幅度上相等,并且产生信号的和和差,这将在精确的正交关系中。

    Direct current power supply conditioning circuit
    8.
    发明授权
    Direct current power supply conditioning circuit 失效
    直流电源调节电路

    公开(公告)号:US5615096A

    公开(公告)日:1997-03-25

    申请号:US254733

    申请日:1994-06-06

    IPC分类号: H01L23/522 H02M3/07 H01L17/00

    摘要: A power supply (200) includes a VVC (222) which provides for the efficient conversion of voltages with minimum ripple. The doping of the VVC (222) is altered such that most of the energy is delivered to a load (224) at a substantially constant voltage. The VVC (222) is fabricated using such materials as Zirconium Titanate. The VVC (222) has a high capacitance to volume ratio and therefore results in a significant reduction in the overall size of the power supply (200).

    摘要翻译: 电源(200)包括VVC(222),其提供具有最小纹波的电压的有效转换。 VVC(222)的掺杂被改变,使得大部分能量以基本恒定的电压被传送到负载(224)。 VVC(222)使用钛酸锆等材料制造。 VVC(222)具有高的电容与体积比,因此导致电源(200)的总体尺寸的显着降低。

    DIRECT DIGITAL SYNTHESIZER WITH VARIABLE REFERENCE FOR IMPROVED SPURIOUS PERFORMANCE
    10.
    发明申请
    DIRECT DIGITAL SYNTHESIZER WITH VARIABLE REFERENCE FOR IMPROVED SPURIOUS PERFORMANCE 有权
    具有可改善性能的可变参考的直接数字合成器

    公开(公告)号:US20080258791A1

    公开(公告)日:2008-10-23

    申请号:US11861860

    申请日:2007-09-26

    IPC分类号: H03H11/26

    摘要: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

    摘要翻译: 改进在有限分辨率的延迟线中出现的量化误差。 包含数控振荡器(NCO)和数字 - 相位转换器(DPC)的直接数字合成器(DDS)放置在锁相环(PLL)的反馈环路中。 DDS用作压控振荡器(VCO)频率的分数分频器,使得DDS的参考频率变为可变。 然后可以调整由DDS延迟线提供的边缘的对准。 通过利用独立的可调谐延迟元件来减少DDS延迟线中的不匹配误差。