摘要:
A parameter extraction technique for an electrical structure is based on a definition of network parameters that isolates pure mode responses of the electrical structure, and that makes mode conversion responses of the electrical structure negligible. A set of network parameters is obtained that represents pure mode responses for the electrical structure (410). These network parameters are processed to obtain model parameters that characterize each pure mode response (422, 424, 426, 428, 432, 434, 436, 438). Preferably, the mode specific parameters to combined to obtain mode independent parameters, such as coupling factor, propagation constant, and characteristic impedance values (440, 450).
摘要:
To reduce crosstalk in reentrant off-chip RF selectivity, differential circuits (402, 415), transmission lines (423, 424), and off-chip filters (422) are used in a structure that balances the parasitic capacitances associated with all of the differential elements. The structure includes a substrate (409) with a differential generating circuit (402) and a receiving circuit (415). Two differential transmission lines (423, 424), each with constant characteristic impedance, and each with balanced capacitance to ground, both being closely spaced for some distance, couple the circuits (402, 415) to closely spaced terminating pads (403). A ground plane (412) is shared under both transmission lines (423, 424). A second substrate (408) having a reentrant RF path (406) with the first substrate (409) contains an RF function such as a filter or a delay line.
摘要:
An electronic circuit (300) includes first (302) and second (304) variable impedance devices coupled together. The first (302) and second (304) variable impedance devices are designed such that each exhibits a transfer function which is substantially inverse with respect to the other about the operating point of the electronic circuit. This provides for an electronic circuit which exhibits very low distortion characteristics. Circuits such as tunable filters, voltage-controlled oscillators (VCOs), receivers, etc. will benefit from using an electronic circuit (300) which exhibits such low distortion characteristics.
摘要:
A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 . . . 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 . . . 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.
摘要:
A differential circuit (200) provides for reverse isolation between input and output ports (202, 204). The differential circuit has amplification circuitry that includes active transistors (221, 222) and reverse isolation circuitry that employ transistors (223,224) having similar manufacturing and processing characteristics to couple the input and output ports (202, 204).
摘要:
An apparatus (100) includes a differential processing circuit (135) responsive to an input signal with first and second signal components, and a signal imbalance suppressor (130) that preprocesses the input signal, prior to input to the differential processing circuit, to remove amplitude and/or phase imbalances that exist between the first and second signal components, in order to reduce even order distortion generation within the differential processing circuit.
摘要:
The invention produces an accurate quadrature relationship for a range of frequencies using passive components in the primary quadrature splitting circuits. A reference oscillator (202) generates a reference signal which is fed to a conventional passive quadrature splitter circuit (204). However, since the reference circuit provides signals over a range of frequencies, the output signals of the passive quadrature splitter may not have an accurate quadrature relationship. The output signals of the passive quadrature splitter are then equalized in magnitude, and the sum and difference of the signals are produced, which will be in an accurate quadrature relationship.
摘要:
A power supply (200) includes a VVC (222) which provides for the efficient conversion of voltages with minimum ripple. The doping of the VVC (222) is altered such that most of the energy is delivered to a load (224) at a substantially constant voltage. The VVC (222) is fabricated using such materials as Zirconium Titanate. The VVC (222) has a high capacitance to volume ratio and therefore results in a significant reduction in the overall size of the power supply (200).
摘要:
A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multiple outputs. A modulating signal can be used in the tap selection processing to produce digital amplitude, frequency and/or phase modulation.
摘要:
Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.