Communication system capable of adjusting transmit power of a subscriber
unit
    1.
    发明授权
    Communication system capable of adjusting transmit power of a subscriber unit 失效
    可调整订阅单位发送功率的通信系统

    公开(公告)号:US5204970A

    公开(公告)日:1993-04-20

    申请号:US648809

    申请日:1991-01-31

    IPC分类号: H04B1/04 H04B7/005 H04B7/26

    摘要: A method for adjusting the transmitter power of a subscriber unit includes the steps of determining noise characteristic of a receiver site, measuring strength of a signal received from the subscriber, determining a power adjust value based on the noise characteristic and the received signal strength. The transmit power of the subscriber unit is adjusted according to the power adjust value.

    摘要翻译: 一种用于调整用户单元的发射机功率的方法包括以下步骤:确定接收站点的噪声特性,测量从用户接收的信号的强度,基于噪声特性和接收信号强度确定功率调整值。 用户单元的发射功率根据功率调整值进行调整。

    DIRECT DIGITAL SYNTHESIZER WITH VARIABLE REFERENCE FOR IMPROVED SPURIOUS PERFORMANCE
    2.
    发明申请
    DIRECT DIGITAL SYNTHESIZER WITH VARIABLE REFERENCE FOR IMPROVED SPURIOUS PERFORMANCE 有权
    具有可改善性能的可变参考的直接数字合成器

    公开(公告)号:US20080258791A1

    公开(公告)日:2008-10-23

    申请号:US11861860

    申请日:2007-09-26

    IPC分类号: H03H11/26

    摘要: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

    摘要翻译: 改进在有限分辨率的延迟线中出现的量化误差。 包含数控振荡器(NCO)和数字 - 相位转换器(DPC)的直接数字合成器(DDS)放置在锁相环(PLL)的反馈环路中。 DDS用作压控振荡器(VCO)频率的分数分频器,使得DDS的参考频率变为可变。 然后可以调整由DDS延迟线提供的边缘的对准。 通过利用独立的可调谐延迟元件来减少DDS延迟线中的不匹配误差。

    Digital-to-time converter using cycle selection windowing
    3.
    发明授权
    Digital-to-time converter using cycle selection windowing 有权
    数字时间转换器采用周期选择窗口

    公开(公告)号:US07409416B2

    公开(公告)日:2008-08-05

    申请号:US11420941

    申请日:2006-05-30

    申请人: Robert E. Stengel

    发明人: Robert E. Stengel

    IPC分类号: G06F1/02

    摘要: A signal generator consistent with certain embodiments of the invention has a reference clock (34) producing a periodic sequence of reference clock output pulses. A window generator (38) generates a plurality of time windows through which a selected plurality of the reference clock output pulses are selectively passed as windowed pulses so that the windowed pulses form a selected pattern of pulses. A programmable delay (46) has resolution of delay that has finer time granularity in delay than the period of the clock output pulses. The programmable delay (46) delays each of the windowed pulses by a programmed delay time to thereby provide a timing correction to the windowed pulses to produce an output pattern of pulses.

    摘要翻译: 与本发明的某些实施例一致的信号发生器具有产生周期性的参考时钟输出脉冲序列的参考时钟(34)。 窗口产生器(38)产生多个时间窗口,所选择的多个参考时钟输出脉冲通过该时间窗口被选择性地作为窗口脉冲通过,使得窗口脉冲形成选定的脉冲图案。 可编程延迟(46)具有延迟分辨率,其延迟时间比时钟输出脉冲的周期更精细。 可编程延迟(46)将每个加窗脉冲延迟编程的延迟时间,从而为加窗脉冲提供定时校正,以产生脉冲的输出模式。

    Dynamically matched mixer system with improved in-phase and quadrature (I/Q) balance and second order intercept point (IP2) performance
    4.
    发明授权
    Dynamically matched mixer system with improved in-phase and quadrature (I/Q) balance and second order intercept point (IP2) performance 有权
    具有改进的同相和正交(I / Q)平衡和二阶截点(IP2)性能的动态匹配混频器系统

    公开(公告)号:US07251468B2

    公开(公告)日:2007-07-31

    申请号:US10890691

    申请日:2004-07-14

    IPC分类号: H04B1/10

    摘要: A dynamically matched mixer system (200) for use in a direct conversion radio frequency (RF) receiver includes a frequency generator (201, 203, 205) that includes plurality of dividers (407) for providing differential local oscillator reference sources (FLO+ and FLO−) and mitigation frequency reference sources (F1 and F2) from reference oscillator (205). A mixer (209) mixes the differential local oscillator reference sources (FLO+ and FLO−) and the mitigation frequency reference sources (F1 and F2) while dynamic matching units (211, 213) are used for receiving the mitigation frequency reference sources and matching switching parameters of differential input signals (IRF+ and IRF−) and differential baseband output signals (IBB+ and IBB−). The frequencies of the mitigation frequency reference sources (F1 and F2) are selected so as to establish a non-integer relationship to the reference oscillator (201) for mitigating the occurrence of interference with FLO+ and FLO−.

    摘要翻译: 用于直接转换射频(RF)接收机的动态匹配混频器系统(200)包括频率发生器(201,203,205),其包括多个分频器(407),用于提供差分本地振荡器参考源(F and and> LO LO LO LO LO LO LO LO)和缓解频率参考源(F 1和F 2) 单元(211,213)用于接收缓解频率参考源和差分输入信号(I + RF +和I + RF - )的匹配切换参数和差分基带输出信号 (I BB +和/或BB - )。 选择缓解频率参考源(F 1和F 2)的频率以便建立与参考振荡器(201)的非整数关系,以便减轻与F LO和/ F

    Method and apparatus for digital frequency synthesis
    5.
    发明授权
    Method and apparatus for digital frequency synthesis 有权
    数字频率合成方法和装置

    公开(公告)号:US06891420B2

    公开(公告)日:2005-05-10

    申请号:US10036558

    申请日:2001-12-21

    CPC分类号: H03L7/22 H03L7/0812 H03L7/16

    摘要: A digital frequency synthesizer includes one or more reference clocks (104, 1316, 1502A, 1504A, 1506A) optionally coupled through one or more pulse width reducers (106) to one or more main delay lines (108, 702, 1502B, 1504B, 1506B) that include a plurality of output taps (108B-108I, 702B-702E). During at least certain periods of the reference clock (104) a plurality of the output taps are coupled to a common output (130, 1312, 1508), thereby producing an output signal that has a frequency that exceeds a frequency of the one or more reference clocks. The coupling is preferably accomplished by transmission gates (114, 128, 720-724, 1420-1434) that are switched by gating pulses that are received from decoders (148, 150, 1418) via gating signal delay lines (134-146, 704-718, 1404-1416).

    摘要翻译: 数字频率合成器包括一个或多个参考时钟(104,1316,1502A,1504A,1506A),其可选地通过一个或多个脉冲宽度减法器(106)耦合到一个或多个主延迟线(108,702,1502B ,1504B,1506B),其包括多个输出抽头(108B-108I,702B-702E)。 在参考时钟(104)的至少某些时段期间,多个输出抽头耦合到公共输出(130,1312,1508),从而产生具有超过一个或多个频率的频率的频率的输出信号 参考时钟。 耦合优选地由通过选通脉冲切换的传输门(114,128,720-724,1420-1434)完成,门脉冲经由选通信号延迟线(134-146,704)从解码器(148,150,1418)接收 -718,1404-1416)。

    Method and apparatus for extracting parameters for an electrical structure
    7.
    发明授权
    Method and apparatus for extracting parameters for an electrical structure 有权
    用于提取电气结构参数的方法和装置

    公开(公告)号:US06539344B1

    公开(公告)日:2003-03-25

    申请号:US09553814

    申请日:2000-04-21

    IPC分类号: G06F760

    CPC分类号: G06F17/5036

    摘要: A parameter extraction technique for an electrical structure is based on a definition of network parameters that isolates pure mode responses of the electrical structure, and that makes mode conversion responses of the electrical structure negligible. A set of network parameters is obtained that represents pure mode responses for the electrical structure (410). These network parameters are processed to obtain model parameters that characterize each pure mode response (422, 424, 426, 428, 432, 434, 436, 438). Preferably, the mode specific parameters to combined to obtain mode independent parameters, such as coupling factor, propagation constant, and characteristic impedance values (440, 450).

    摘要翻译: 用于电气结构的参数提取技术基于隔离电气结构的纯模式响应的网络参数的定义,并且使得电气结构的模式转换响应可忽略不计。 获得代表电结构(410)的纯模式响应的一组网络参数。 处理这些网络参数以获得表征每个纯模式响应(422,424,426,428,432,434,436,438)的模型参数。 优选地,组合的模式特定参数以获得模式无关参数,例如耦合因子,传播常数和特征阻抗值(440,450)。

    Efficient amplitude/phase modulation amplifier
    9.
    发明授权
    Efficient amplitude/phase modulation amplifier 失效
    高效振幅/相位调制放大器

    公开(公告)号:US5329259A

    公开(公告)日:1994-07-12

    申请号:US986823

    申请日:1993-02-11

    IPC分类号: H03F3/60 H04L27/36

    摘要: A high efficiency amplitude/phase modulation amplifier circuit (100) includes a first (102) and a second (106) high efficiency amplifier. These amplifiers (102 and 106) amplify two constant amplitude/phase modulated signals. A combiner (104) combines the output signals from the amplifiers (102) and (106) to produce a combined signal to a load (108). Two shunt elements (202 and 204) are included to prevent the reactive components of the combined signal from reaching the amplifiers (102) and (106). With no reactive components reflected back, the amplifiers (102 and 106) can remain non-linear even though they are used to amplify an amplitude/phase modulated signal which includes Amplitude Modulation (AM) components.

    摘要翻译: 高效率幅度/相位调制放大器电路(100)包括第一(102)和第二(106)高效放大器。 这些放大器(102和106)放大两个恒定幅度/相位调制信号。 组合器(104)组合来自放大器(102)和(106)的输出信号以产生到负载(108)的组合信号。 包括两个并联元件(202和204)以防止组合信号的无功分量到达放大器(102)和(106)。 由于没有反射的分量反射回,放大器(102和106)可以保持非线性,即使它们被用于放大包括幅度调制(AM)分量的幅度/相位调制信号。

    Integrated distributed inductive-capacitive network
    10.
    发明授权
    Integrated distributed inductive-capacitive network 失效
    集成分布式感性电容网络

    公开(公告)号:US5283462A

    公开(公告)日:1994-02-01

    申请号:US787431

    申请日:1991-11-04

    申请人: Robert E. Stengel

    发明人: Robert E. Stengel

    IPC分类号: H01L29/93 H03H1/00

    CPC分类号: H01L29/93 H03H1/00

    摘要: An integrated-distributed-inductive-capacitive network (100) having a high dielectric electronically-tunable semiconductor integrated capacitor. The network (100) also includes a conductive layer (126) formed on the high dielectric semiconductor integrated capacitor, to provide the distributed resistance of the network (100). External contact to the network (100) is provided via a plurality of contact terminals (122A and 122B) which are coupled to the conductive layer (126).

    摘要翻译: 具有高电介质电子可调谐半导体集成电容器的集成分布式感应电容网络(100)。 网络(100)还包括形成在高介电半导体集成电容器上的导电层(126),以提供网络(100)的分布式电阻。 经由耦合到导电层(126)的多个接触端子(122A和122B)提供与网络(100)的外部接触。