公开(公告)号：US07977975B1

公开(公告)日：2011-07-12

申请号：US12563088

申请日：2009-09-18

申请人： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

发明人： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

IPC分类号： H03K19/00

CPC分类号： H03K3/356008 ,  H03K3/0375 ,  H03K19/00315 ,  H03K19/17764

摘要： An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

摘要翻译： 集成电路（IC）包括一组亚稳态硬化存储电路。 每个亚硬化存储电路可以包括：（a）脉冲宽度失真电路; （b）由标称电源电压供电的第一电路和由高于标称电源电压供电的第二电路; （c）逆变器和偏置电路，其中所述偏置电路基于所述逆变器的中间状态提供偏置电流以解决所述逆变器的亚稳态; 或（d）锁存器和动态偏置电路，其使电流注入到锁存器中以解决闩锁的亚稳态。

公开(公告)号：US07712067B1

公开(公告)日：2010-05-04

申请号：US11879912

申请日：2007-07-19

申请人： Ryan Fung ,  Michael Chan

发明人： Ryan Fung ,  Michael Chan

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A method for connecting a first and second component in a logic device is disclosed. A path is generated between the first and second components with an appropriate amount of delay to satisfy short-path timing constraints that define a minimum delay on the path. A first interconnect line from a plurality of interconnect lines and a second interconnect line to connect with the first interconnect line sub-optimally from a delay minimization perspective are selected in order to satisfy the short-path timing constraints.

摘要翻译： 公开了一种在逻辑器件中连接第一和第二部件的方法。 在第一和第二分量之间产生具有适当延迟量的路径以满足在路径上定义最小延迟的短路时序约束。 选择来自多个互连线的第一互连线和从延迟最小化角度次优化地与第一互连线连接的第二互连线，以便满足短路时序约束。

公开(公告)号：US07694256B1

公开(公告)日：2010-04-06

申请号：US11899097

申请日：2007-09-04

申请人： David Galloway ,  Ryan Fung

发明人： David Galloway ,  Ryan Fung

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5054 ,  G06F17/5072 ,  G06F2217/64

摘要： A method for designing a system on a target device having restricted areas includes determining locations on the target device for all cells in the system by solving one or more equations. Partitioning of cells of a first classification type is performed. One or more equations are modified in response to the partitioning. Revised locations on the target device are determined for the cells by solving the modified one or more equations. The partitioning procedure takes into consideration the classification types of cells as well as restricted areas on the target device.

摘要翻译： 用于在具有受限区域的目标设备上设计系统的方法包括通过求解一个或多个等式来确定目标设备上系统中所有单元的位置。 执行第一分类类型的单元的分区。 响应于分区修改一个或多个等式。 通过求解修正的一个或多个方程，为单元确定目标设备上的修正位置。 分区过程考虑到目标设备上的小区的分类类型以及限制区域。

公开(公告)号：US08949763B1

公开(公告)日：2015-02-03

申请号：US12242365

申请日：2008-09-30

申请人： Ryan Fung

发明人： Ryan Fung

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/84

摘要： A system for computer-aided design (CAD) of an integrated circuit (IC) uses a computer. The computer is configured to optimize placement, routing, and/or region configuration of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC).

摘要翻译： 集成电路（IC）的计算机辅助设计（CAD）系统使用计算机。 计算机被配置为通过使集成电路（IC）中的多个低功率区域最大化来优化集成电路（IC）的布局，布线和/或区域配置。

公开(公告)号：US08930597B1

公开(公告)日：2015-01-06

申请号：US13151245

申请日：2011-06-01

申请人： Ryan Fung ,  Christine Lau ,  Kalen B. Brunham

发明人： Ryan Fung ,  Christine Lau ,  Kalen B. Brunham

IPC分类号： G06F13/28 ,  G06F3/00 ,  G06F13/00 ,  G06F5/00 ,  G06F12/06 ,  H04J3/02 ,  H04J3/22

CPC分类号： G06F13/1689

摘要： An external memory interface includes an input/output (IO) logic unit operable to convert a rate of data from a first rate corresponding to a memory controller/schedule unit to a second rate corresponding to an external memory device. The external memory interface also includes a latency adjustment unit, operating in a timing domain of the memory controller/schedule unit, operable to add between 1 to [(second rate/first rate)−1] cycles of latency of the second rate.

摘要翻译： 外部存储器接口包括输入/​​输出（IO）逻辑单元，用于将对应于存储器控制器/调度单元的第一速率的数据速率转换成对应于外部存储器件的第二速率。 外部存储器接口还包括在存储器控制器/调度单元的定时域中操作的等待时间调整单元，其可操作以在第二速率的1到（（第二速率/第一速率）-1]周期之间加上。

公开(公告)号：US08508254B2

公开(公告)日：2013-08-13

申请号：US13149774

申请日：2011-05-31

申请人： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

发明人： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

IPC分类号： H03K19/00

CPC分类号： H03K3/356008 ,  H03K3/0375 ,  H03K19/00315 ,  H03K19/17764

摘要： An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

公开(公告)号：US09697309B1

公开(公告)日：2017-07-04

申请号：US12563095

申请日：2009-09-18

申请人： Ryan Fung ,  David Lewis ,  David Neto

发明人： Ryan Fung ,  David Lewis ,  David Neto

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036 ,  G06F17/5054 ,  H03K3/0375

摘要： An integrated circuit (IC) includes a metastability-hardened synchronization circuit. The metastability-hardened synchronization circuit includes a plurality of sampling circuits, and a multiplexer. The sampling circuits sample an input signal to generate a plurality of sampled signals. The multiplexer generates an output signal from the plurality of sampled signals.

公开(公告)号：US08929162B1

公开(公告)日：2015-01-06

申请号：US13531430

申请日：2012-06-22

申请人： Joshua David Fender ,  Gordon Raymond Chiu ,  Ryan Fung

发明人： Joshua David Fender ,  Gordon Raymond Chiu ,  Ryan Fung

IPC分类号： G11C7/22 ,  G11C7/10

CPC分类号： G11C7/1051 ,  G11C7/1066

摘要： In a memory interface circuit (e.g., a programmable logic device), a clock or strobe (DQS) signal can be gated using a clock-like signal that can also be used to sample the DQS signal. Furthermore, both the rising and falling edges of the DQS signal can be sampled using the clock-like signal.

摘要翻译： 在存储器接口电路（例如，可编程逻辑器件）中，时钟或选通（DQS）信号可以使用也可用于采样DQS信号的类似时钟的信号来选通。 此外，可以使用类似时钟的信号对DQS信号的上升沿和下降沿进行采样。

公开(公告)号：US08904331B1

公开(公告)日：2014-12-02

申请号：US13537115

申请日：2012-06-29

申请人： Ryan Fung

发明人： Ryan Fung

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031 ,  G06F2217/84

摘要： A method for modeling jitter includes generating a first delay-impacting parameter function for a first signal and a second delay-impacting parameter function for a second signal. A first delay per element function is generated from the first delay-impacting parameter function and a second delay per element function from the second delay-impacting parameter function. A difference in path delay from the first delay per element function and the second delay per element function is identified.

摘要翻译： 一种用于对抖动进行建模的方法包括为第一信号产生第一延迟影响参数函数和为第二信号产生第二延迟影响参数函数。 从第一延迟影响参数函数产生第一个每个元素的延迟函数，并且从第二个延迟影响参数函数产生每个元素函数的第二个延迟。 识别从每个元素函数的第一延迟和每个元素函数的第二延迟的路径延迟的差异。

公开(公告)号：US08588014B1

公开(公告)日：2013-11-19

申请号：US13149583

申请日：2011-05-31

申请人： Ryan Fung ,  Valavan Manohararajah

发明人： Ryan Fung ,  Valavan Manohararajah

IPC分类号： G11C7/00

CPC分类号： G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  H03K5/131 ,  H03K19/17744

摘要： Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

摘要翻译： 可以提供具有存储器接口电路的集成电路。 在校准之前，可以通过计算不同程度的过采样的时间窗口边缘不对称的函数的概率密度函数曲线来确定多个样本。 在校准期间，可以通过选择性地延迟数据选通上升沿或下降沿来校正数据选通信号中的占空比失真。 用于产生数据信号的数据时钟信号也可能遭受占空比失真。 可以选择性地延迟数据时钟信号的上升沿和下降沿以校正占空比失真。 可以调整数据信号路由的数据路径以均衡上升和下降转换，以最小化数据路径占空比失真。 可以通过校准到允许每个存储器等级通过存储器操作测试的成功设置的交集来执行多级校准。