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    CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES
    31.
    发明申请
    CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES 有权

    公开(公告)号：US20210358553A1

    公开(公告)日：2021-11-18

    申请号：US17360572

    申请日：2021-06-28

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

    Abstract: Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

    PROGRAMMING PROCESS WHICH COMPENSATES FOR DATA STATE OF ADJACENT MEMORY CELL IN A MEMORY DEVICE
    35.
    发明申请
    PROGRAMMING PROCESS WHICH COMPENSATES FOR DATA STATE OF ADJACENT MEMORY CELL IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20200312415A1

    公开(公告)日：2020-10-01

    申请号：US16901077

    申请日：2020-06-15

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang

    IPC: G11C16/34 ,  G11C16/16 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C11/56 ,  G11C7/10

    Abstract: Techniques are provided to compensate for neighbor word line interference when programming memory cells connected to a selected word line WLn. Before programming, the assigned data states of WLn and WLn+1 are compared and corresponding compensation data is generated. The compensation data may be stored in latches of sense circuits to modify the verify tests which occur during programming. The compensation can involve adjusting the bit line voltage, word line voltage, sense node discharge period and/or trip voltage. During a verify test, the compensation data can cause a WLn memory cell to complete programming when its threshold voltage is lower than would be the case with no compensation. When the WLn+1 memory cells are subsequently programmed, an upshift in the threshold voltage of the WLn memory cell offsets the compensation.

    PROGRAMMING PROCESS COMBINING ADAPTIVE VERIFY WITH NORMAL AND SLOW PROGRAMMING SPEEDS IN A MEMORY DEVICE
    36.
    发明申请
    PROGRAMMING PROCESS COMBINING ADAPTIVE VERIFY WITH NORMAL AND SLOW PROGRAMMING SPEEDS IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20200303025A1

    公开(公告)日：2020-09-24

    申请号：US16893626

    申请日：2020-06-05

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

    IPC: G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

    Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.

    Bias scheme for dummy lines of data storage devices
    38.
    发明授权
    Bias scheme for dummy lines of data storage devices 有权

    公开(公告)号：US10726923B2

    公开(公告)日：2020-07-28

    申请号：US16198593

    申请日：2018-11-21

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/28 ,  G11C11/56 ,  G11C16/24 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519

    Abstract: Systems and methods reduce latency during read-verify and programming operations by biasing a dummy line next to a neighboring bit line with an over-drive voltage during a first period and then biasing the dummy line to a same voltage as that of the neighboring bit line during a second period that contiguously follows the first period. The dummy line may be biased based on a state of the neighboring bit line. For example, a first dummy line is first charged to an over-drive voltage and then charged to the same voltage as that of a first neighboring bit line, and a second dummy line at an opposing edge is first charged to the over-drive voltage and then charged to the same voltage as that of a second neighboring bit line. This biasing scheme using the dummy lines helps reduce capacitive loading for neighboring bit lines during ready-verify and programming operations.

    Mitigating Grown Bad Blocks
    39.
    发明申请
    Mitigating Grown Bad Blocks 审中-公开

    公开(公告)号：US20200211652A1

    公开(公告)日：2020-07-02

    申请号：US16236792

    申请日：2018-12-31

    Applicant: SanDisk Technologies LLC

    Inventor： Jianzhi Wu ,  Xiang Yang ,  Jun Wan

    IPC: G11C16/16 ,  G11C29/00 ,  G06F3/06 ,  G06F12/02

    Abstract: Example techniques that mitigate against memory hole shorts during an erase operation for memory cells in a string include an example method in which, during an erase operation, erase pulses are applied to the word lines of the memory string and terminated at different times based. In some instances, the erase pulses applied to the word lines of the memory string are terminated based on the temperature of the memory cells of the memory string. In further implementations, the erase pulses applied to the word lines of the memory string are boosted for different times depending on the location of the word line along the memory string during the erase operation.

    NON-VOLATILE MEMORY WITH COUNTERMEASURES FOR SELECT GATE DISTURB DURING PROGRAM PRE-CHARGE
    40.
    发明申请
    NON-VOLATILE MEMORY WITH COUNTERMEASURES FOR SELECT GATE DISTURB DURING PROGRAM PRE-CHARGE 审中-公开

    公开(公告)号：US20200051648A1

    公开(公告)日：2020-02-13

    申请号：US16056838

    申请日：2018-08-07

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang

    IPC: G11C16/34 ,  G11C5/02 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/04 ,  G11C16/28 ,  G11C7/12 ,  G11C8/08

    Abstract: Program disturb is a condition that includes the unintended programming while performing a programming process for memory cells, where the program disturb can affect both memory cells and select gates in a NAND structure. During a pre-charge phase of a programming operation, a drain side select gate may be biased to a higher voltage than an adjacent word line, resulting in a disturb of the select gate due to hot-electron injection. This can raise the threshold voltage of the select gate, causing error in reading the NAND string or even making it inaccessible. To help avoid this problem, during a program pre-charge, the voltage applied to the select gate is raised in a sequence of steps, rather than driving the select gate directly to its final pre-charge voltage level.

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