公开(公告)号：US11798625B2

公开(公告)日：2023-10-24

申请号：US17469016

申请日：2021-09-08

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Gerrit Jan Hemink

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C11/5671 ,  H10B43/10 ,  H10B43/27

Abstract: An apparatus includes a control circuit configured to connect to first word lines of a first vertical sub-block and second word lines of a second vertical sub-block. The first vertical sub-block and the second vertical sub-block include memory cells connected in series in NAND strings, each NAND string including memory cells coupled to the first word lines in series with memory cells connected to the second word lines. The control circuit is configured to program or sense memory cells along a selected first word line of the first vertical sub-block while applying a first voltage to second word lines that are connected to programmed memory cells and applying a second voltage to second word lines that are connected to unprogrammed memory cells.

公开(公告)号：US20230050955A1

公开(公告)日：2023-02-16

申请号：US17399498

申请日：2021-08-11

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Gerrit Jan Hemink ,  Xiang Yang ,  Ken Oowada ,  Guirong Liang

IPC: G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

Abstract: To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.

公开(公告)号：US11545221B2

公开(公告)日：2023-01-03

申请号：US17360572

申请日：2021-06-28

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

Abstract: Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

公开(公告)号：US20220404989A1

公开(公告)日：2022-12-22

申请号：US17349306

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G06F3/06

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

公开(公告)号：US20200303459A1

公开(公告)日：2020-09-24

申请号：US16896946

申请日：2020-06-09

Applicant: SanDisk Technologies LLC

Inventor： Federico Nardi ,  Christopher J. Petti ,  Gerrit Jan Hemink

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  G11C11/56

Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

公开(公告)号：US10304551B2

公开(公告)日：2019-05-28

申请号：US15194295

申请日：2016-06-27

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Mohan Dunga ,  Gerrit Jan Hemink ,  Changyuan Chen

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for erase depth control. One apparatus includes a block of non-volatile storage cells. A controller is configured to perform a first erase operation on a block of non-volatile storage cells. A controller for a block is configured to determine a first set of storage cells of the block having a faster erase speed than a second set of storage cells of the block based on a verify voltage threshold. A controller for a block is configured to perform a second erase operation on the block using different voltages for a first set of storage cells and a second set of storage cells of the block.

公开(公告)号：US10008273B2

公开(公告)日：2018-06-26

申请号：US15181346

申请日：2016-06-13

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Gerrit Jan Hemink ,  Mohan Dunga ,  Bijesh Rajamohanan ,  Changyuan Chen

IPC: G11C16/28 ,  G06F11/10 ,  G11C29/52 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C29/02 ,  G11C7/12 ,  G11C29/12

CPC classification number: G11C16/28 ,  G06F11/1068 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/1204

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.

公开(公告)号：US11887677B2

公开(公告)日：2024-01-30

申请号：US17701365

申请日：2022-03-22

Applicant: SanDisk Technologies LLC

Inventor： Muhammad Masuduzzaman ,  Deepanshu Dutta ,  Gerrit Jan Hemink

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  H10B41/27 ,  H10B43/27

Abstract: The memory device includes a controller that is configured to program the memory cells of a selected word line in a plurality of program-verify iterations. During a verify portion at least one of the program-verify iterations, the controller determines a threshold voltage of at least one memory cell relative to a first verify low voltage VL1, a second verify low voltage VL2, and a verify high voltage VH associated with a data state being programmed. The controller also maintains a count of program-verify iterations since the at least one memory cell passed a verify high voltage of a previously programmed data state or discharges a sense node through a channel including the at least one memory cell and compares a discharge time to predetermined sense times associated with the first and second verify low voltages and with the verify high voltage.

公开(公告)号：US20230326506A1

公开(公告)日：2023-10-12

申请号：US17718759

申请日：2022-04-12

Applicant: SanDisk Technologies LLC

Inventor： Michael Grobis ,  James W. Reiner ,  Michael Nicolas Albert Tran ,  Juan P. Saenz ,  Gerrit Jan Hemink

IPC: G11C11/16 ,  G11C7/20 ,  G11C13/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: G11C11/1659 ,  G11C7/20 ,  G11C13/003 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/1443

Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test. Techniques are also presented for initializing a cross-point array, for both first fire and cold start, by using voltage levels shifted from half-select voltage levels used in a standard memory access.

公开(公告)号：US11688469B2

公开(公告)日：2023-06-27

申请号：US17399498

申请日：2021-08-11

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Gerrit Jan Hemink ,  Xiang Yang ,  Ken Oowada ,  Guirong Liang

IPC: G11C16/04 ,  G11C16/34 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L25/065

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2225/06506 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.