公开(公告)号：US20190392893A1

公开(公告)日：2019-12-26

申请号：US16019456

申请日：2018-06-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Dengtao Zhao ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Zhongguang Xu ,  Yanli Zhang ,  Jin Liu

IPC: G11C11/56 ,  G11C16/24 ,  G11C16/08 ,  G11C16/14 ,  G11C16/34 ,  G11C16/04

Abstract: Non-volatile memory strings may include multiple selection devices for coupling memory cell devices to a bit line. Different programming operations may be used to program various individual selection devices in a non-volatile memory cells string. For example, a control circuit may set a threshold voltage of a particular selection device to a value greater than a threshold voltage of another selection device. In another example, the control circuit may program the selection device using an initial sense time. Subsequent to programming the selection device using the initial sense time, the control circuit may program the selection device using a different sense time that is shorter than the initial sense time.

公开(公告)号：US20170179151A1

公开(公告)日：2017-06-22

申请号：US15268946

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Jin Liu ,  Johann Alsmeier ,  Jixin Yu ,  Yoko Furihata ,  Hiroyuki Ogawa

IPC: H01L27/115 ,  H01L21/768 ,  H01L27/02 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US10453854B2

公开(公告)日：2019-10-22

申请号：US15813625

申请日：2017-11-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshihiro Kanno ,  Senaka Krishna Kanakamedala ,  Raghuveer S. Makala ,  Yanli Zhang ,  Jin Liu ,  Murshed Chowdhury

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

公开(公告)号：US20180006054A1

公开(公告)日：2018-01-04

申请号：US15707842

申请日：2017-09-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jin Liu ,  Chun Ge ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11529

CPC classification number: H01L27/11582 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate adjacent to the memory hole.

公开(公告)号：US09818759B2

公开(公告)日：2017-11-14

申请号：US15268946

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Jin Liu ,  Johann Alsmeier ,  Jixin Yu ,  Yoko Furihata ,  Hiroyuki Ogawa

IPC: H01L27/115 ,  H01L21/768 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US20170179026A1

公开(公告)日：2017-06-22

申请号：US15269017

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumiaki Toyama ,  Hiroyuki Ogawa ,  Yoko Furihata ,  James Kai ,  Yuki Mizutani ,  Jixin Yu ,  Jin Liu ,  Johann Alsmeier

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US09818693B2

公开(公告)日：2017-11-14

申请号：US15269017

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumiaki Toyama ,  Hiroyuki Ogawa ,  Yoko Furihata ,  James Kai ,  Yuki Mizutani ,  Jixin Yu ,  Jin Liu ,  Johann Alsmeier

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US20170148810A1

公开(公告)日：2017-05-25

申请号：US15225492

申请日：2016-08-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Johann Alsmeier ,  Jin Liu ,  Yanli Zhang

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/768 ,  H01L29/423 ,  H01L23/535 ,  H01L21/306

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/30604 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42344

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. An alternating sequence of support pedestal structures and conductive rail structures extending along a same horizontal direction are provided between the substrate and the alternating stack. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support pedestal structure. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure, and is electrically isolated from an adjacent support pedestal structure by a portion of a memory film. The conductive rail structures can function as source regions of memory device.

公开(公告)号：US10461163B2

公开(公告)日：2019-10-29

申请号：US15813579

申请日：2017-11-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Senaka Krishna Kanakamedala ,  Yoshihiro Kanno ,  Raghuveer S. Makala ,  Yanli Zhang ,  Jin Liu ,  Murshed Chowdhury ,  Yao-Sheng Lee

IPC: H01L29/423 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/49 ,  H01L29/66 ,  H01L23/522

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

公开(公告)号：US10038006B2

公开(公告)日：2018-07-31

申请号：US15269294

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoko Furihata ,  Jixin Yu ,  Hiroyuki Ogawa ,  James Kai ,  Jin Liu ,  Johann Alsmeier

IPC: H01L29/76 ,  H01L29/792 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/02

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.