公开(公告)号：US20230040826A1

公开(公告)日：2023-02-09

申请号：US17758624

申请日：2020-12-15

Applicant: Soitec

Inventor： Gweltaz Gaudin ,  Céline Futin

IPC: H01L21/18 ,  H01L21/324

Abstract: The disclosure relates to a method of joining two semi-conductor substrates by molecular adhesion comprising: a step a) of bringing a first and a second substrate into intimate contact in order to form an assembly having a bonding interface; a step b) of reaction-annealing the bonding interface at a first temperature higher than a predetermined first temperature, this step b) generating bubbles at the joining interface; a step c) of at least partially debonding the two substrates at the bonding interface in order to eliminate the bubbles; and a step d) of bringing the first and the second substrate into intimate contact at the bonding interface in order to reform the assembly.

公开(公告)号：US11239108B2

公开(公告)日：2022-02-01

申请号：US17043480

申请日：2019-03-22

Applicant: Soitec

Inventor： Gweltaz Gaudin ,  Didier Landru ,  Bruno Ghyselen

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/768

Abstract: A process for producing a donor substrate for creating a three-dimensional integrated structure comprises the following steps: providing a semiconductor substrate comprising a surface layer, referred to as an active layer, and a layer comprising a plurality of cavities extending beneath the active layer, each cavity being separated from an adjacent cavity by a partition, forming an electronic device in a region of the active layer located plumb with a cavity, depositing a protective mask on the active layer so as to cover the electronic device while at the same time exposing a region of the active layer located plumb with each partition, and implanting atomic species through regions of the active layer exposed by the mask to form a weakened zone in each partition.

公开(公告)号：US11156778B2

公开(公告)日：2021-10-26

申请号：US16323238

申请日：2017-07-27

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Gweltaz Gaudin

IPC: H01L21/76 ,  G02B6/132 ,  G02B6/136 ,  H01L21/762

Abstract: A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.

公开(公告)号：US20210057268A1

公开(公告)日：2021-02-25

申请号：US17043480

申请日：2019-03-22

Applicant: Soitec

Inventor： Gweltaz Gaudin ,  Didier Landru ,  Bruno Ghyselen

IPC: H01L21/762 ,  H01L21/768

Abstract: A process for producing a donor substrate for creating a three-dimensional integrated structure comprises the following steps: providing a semiconductor substrate comprising a surface layer, referred to as an active layer, and a layer comprising a plurality of cavities extending beneath the active layer, each cavity being separated from an adjacent cavity by a partition, forming an electronic device in a region of the active layer located plumb with a cavity, depositing a protective mask on the active layer so as to cover the electronic device while at the same time exposing a region of the active layer located plumb with each partition, and implanting atomic species through regions of the active layer exposed by the mask to form a weakened zone in each partition.

公开(公告)号：US20150132923A1

公开(公告)日：2015-05-14

申请号：US14360124

申请日：2012-11-21

Applicant: Soitec

Inventor： Gweltaz Gaudin

IPC: H01L21/762 ,  H01L21/265 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/76251 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/26513 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/76254

Abstract: The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising: bonding a first substrate made of a single-crystal first material, the first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate; removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate.

Abstract translation: 本发明涉及一种用于制造异质结构的方法，该方法包括由半导体制成的至少一个薄层和载体衬底，所述方法包括：将由单晶第一材料制成的第一衬底接合，所述第一衬底包括形成的表面层 多晶第二材料的第二基板，以便在所述多晶层和所述第二基板之间形成接合界面; 从称为供体基板的一个基板的自由表面去除其厚度，使得仅保留薄层; 通过所述多晶材料层的非晶化在所述第一基板和所述接合界面之间产生非晶半导体材料层; 并且使非晶半导体材料层结晶，所述新结晶层具有与相邻的第一衬底相同的取向。

公开(公告)号：US08999090B2

公开(公告)日：2015-04-07

申请号：US13749471

申请日：2013-01-24

Applicant: SOITEC

Inventor： Gweltaz Gaudin ,  Fabrice Lallement ,  Cyrille Colnat ,  Pascale Giard

IPC: B32B37/00 ,  H01L21/18 ,  H01L21/67 ,  H01L21/762

CPC classification number: H01L21/187 ,  H01L21/67092 ,  H01L21/76251 ,  Y10T156/10

Abstract: The invention relates to a method for bonding two substrates, in particular, two semiconductor substrates that, in order to be able to improve the reliability of the process, provides the step of providing a gaseous flow over the bonding surfaces of the substrates. The gaseous flow is preferably a laminar flow that is essentially parallel to the bonding surfaces of the substrates, and has a temperature in a range of from room temperature up to 100° C.

Abstract translation: 本发明涉及一种用于接合两个基板，特别是两个半导体基板的方法，为了能够提高该工艺的可靠性，提供了在基板的接合表面上提供气流的步骤。 气流优选是基本上平行于基板的粘合表面的层流，并且具有在室温至100℃的范围内的温度。

公开(公告)号：US20130139946A1

公开(公告)日：2013-06-06

申请号：US13749471

申请日：2013-01-24

Applicant: SOITEC

Inventor： Gweltaz Gaudin ,  Fabrice Lallement ,  Cyrille Colnat ,  Pascale Giard

IPC: H01L21/18

CPC classification number: H01L21/187 ,  H01L21/67092 ,  H01L21/76251 ,  Y10T156/10

Abstract: The invention relates to a method for bonding two substrates, in particular two semiconductor substrates which, in order to be able to improve the reliability of the process, provides the step of providing a gaseous flow over the bonding surfaces of the substrates. The gaseous flow is preferably a laminar flow that is essentially parallel to the bonding surfaces of the substrates, and has a temperature in a range of from room temperature up to 100° C.

Abstract translation: 本发明涉及一种用于接合两个基板，特别是两个半导体基板的方法，为了能够提高该工艺的可靠性，提供了在基板的接合表面上提供气流的步骤。 气流优选是基本上平行于基板的粘合表面的层流，并且具有在室温至100℃的范围内的温度。