METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

    公开(公告)号:US20190187376A1

    公开(公告)日:2019-06-20

    申请号:US16323238

    申请日:2017-07-27

    Applicant: Soitec

    CPC classification number: G02B6/132 G02B6/136 H01L21/76251

    Abstract: A method for manufacturing a semiconductor structure and to a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.

    Method for transferring a layer comprising a compressive stress layer and related structures
    2.
    发明授权
    Method for transferring a layer comprising a compressive stress layer and related structures 有权
    用于转移包含压应力层和相关结构的层的方法

    公开(公告)号:US09548237B2

    公开(公告)日:2017-01-17

    申请号:US14377738

    申请日:2013-01-28

    Applicant: Soitec

    Abstract: A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement region. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region.

    Abstract translation: 一种包括以下步骤的方法:提供支撑衬底和供体衬底,在所述供体衬底中形成脆化区域,以限定所述脆化区域的任一侧上的第一部分和第二部分,将所述施主衬底组装在所述支撑体上 底物,沿着脆化区域压裂施主衬底。 此外,该方法包括在施主衬底中形成压应力层以限定介于压应力层和脆化区之间的所谓约束区的步骤。

    Method for sealing cavities using membranes

    公开(公告)号:US12234144B2

    公开(公告)日:2025-02-25

    申请号:US17637040

    申请日:2020-08-18

    Abstract: A method for sealing cavities using membranes, the method including a) forming cavities arranged in a matrix, of a depth p, a characteristic dimension a, and spaced apart by a spacing b; and b) forming membranes, sealing the cavities, by transferring a sealing film. The method further includes a step a1), executed before step b), of forming a first contour on the front face and/or on the sealing face, the first contour comprising a first trench having a width L and a first depth p1, the formation of the first contour being executed such that after step b) the cavities are circumscribed by the first contour, said first contour being at a distance G from the cavities between one-fifth of b and five b.

    COMPOSITE STRUCTURE COMPRISING A USEFUL MONOCRYSTALLINE SIC LAYER ON A POLYCRYSTALLINE SIC CARRIER SUBSTRATE AND METHOD FOR MANUFACTURING SAID STRUCTURE

    公开(公告)号:US20240395603A1

    公开(公告)日:2024-11-28

    申请号:US18694369

    申请日:2022-09-20

    Applicant: Soitec

    Abstract: A method for manufacturing a composite structure having a layer of monocrystalline silicon carbide on a polycrystalline silicon carbide carrier substrate includes: providing an initial substrate of polycrystalline silicon carbide, having a front face and comprising grains, the average size of which is greater than 0.5 μm; forming a polycrystalline silicon carbide surface layer on the initial substrate to form the carrier substrate, the surface layer including grains having an average size of less than 500 nm and having a thickness of between 50 nm and 50 μm; preparing a free surface of the surface layer of the carrier substrate to obtain a roughness of less than 1 nm RMS; (d) a step of transferring the useful layer onto the carrier substrate, by applying molecular bonding, the surface layer located between the useful layer and the initial substrate. A carrier substrate and a composite structure are formed by the method.

    METHOD FOR TRANSFERRING A MONOCRYSTALLINE SIC LAYER ONTO A POLYCRYSTALLINE SIC CARRIER USING A POLY CRYSTALLINE SIC INTERMEDIATE LAYER

    公开(公告)号:US20240392476A1

    公开(公告)日:2024-11-28

    申请号:US18694796

    申请日:2022-10-03

    Applicant: Soitec

    Abstract: A method of fabricating a composite structure including a thin layer of single-crystal silicon carbide on a polycrystalline SiC carrier substrate includes: forming a polycrystalline SiC layer on a donor substrate, at least a surface portion of which is made of single-crystal SiC; before or after forming the polycrystalline SiC layer, implanting ionic species into the surface portion of the donor substrate, so as to form a plane of weakness delimiting a thin single-crystal SiC layer to be transferred; after the implanting of the ionic species and the forming of the polycrystalline SiC layer, bonding the donor substrate and the polycrystalline SiC carrier substrate, the polycrystalline SiC layer being at the bonding interface; and detaching the donor substrate along the plane of weakness, so as to transfer the polycrystalline SiC layer and the thin single-crystal SiC layer onto the polycrystalline SiC carrier substrate.

    METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

    公开(公告)号:US20230129131A1

    公开(公告)日:2023-04-27

    申请号:US17452197

    申请日:2021-10-25

    Applicant: Soitec

    Abstract: A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.

    Hybrid structure for a surface acoustic wave device

    公开(公告)号:US11159140B2

    公开(公告)日:2021-10-26

    申请号:US16313804

    申请日:2017-06-26

    Applicant: Soitec

    Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a free first surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer. The hybrid structure further comprises a trapping layer disposed between the useful layer and the support substrate, and at least one functional interface of predetermined roughness between the useful layer and the trapping layer.

    METHOD FOR PRODUCING COMPOSITE STRUCTURE WITH METAL/METAL BONDING
    10.
    发明申请
    METHOD FOR PRODUCING COMPOSITE STRUCTURE WITH METAL/METAL BONDING 有权
    用金属/金属结合生产复合结构的方法

    公开(公告)号:US20150179603A1

    公开(公告)日:2015-06-25

    申请号:US14411741

    申请日:2013-06-05

    Applicant: Soitec

    Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa. The method further comprises, after the step of initiating the propagation of a bonding wave, a step of determining the level of stress induced during bonding of the two wafers, the level of stress being determined on the basis of a stress parameter Ct calculated using the formula Ct=Rc/Ep, where: Rc corresponds to the radius of curvature (in km) of the two-wafer assembly and Ep corresponds to the thickness (in μm) of the two-wafer assembly. The method further comprises a step of validating the bonding when the level of stress Ct determined is greater than or equal to 0.07.

    Abstract translation: 一种制造复合结构的方法,包括至少一个第一晶片与第二晶片的直接结合,并且包括启动键合波的传播的步骤,其中在所述第一和第二晶片传播之后的所述第一和第二晶片之间的结合界面 波具有小于或等于0.7J / m 2的结合能。 启动粘合波传播的步骤是在以下一个或多个条件下进行的:将晶片放置在小于20毫巴的压力的环境中和/或施加到两个晶片之一的机械压力 在0.1MPa和33.3MPa之间。 该方法还包括在开始粘合波的传播的步骤之后,确定在两个晶片的接合期间引起的应力水平的步骤,根据使用第二晶片计算出的应力参数Ct来确定应力水平 公式Ct = Rc / Ep,其中:Rc对应于两晶片组件的曲率半径(km),Ep对应于两晶片组件的厚度(μm)。 该方法还包括当确定的应力Ct大于或等于0.07时验证接合的步骤。

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