公开(公告)号：US09793312B1

公开(公告)日：2017-10-17

申请号：US15230055

申请日：2016-08-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/148 ,  H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14603 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14638 ,  H01L27/14689

Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

公开(公告)号：US20170194368A1

公开(公告)日：2017-07-06

申请号：US15392032

申请日：2016-12-28

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Francois Roy ,  Boris Rodrigues ,  Marie Guillon ,  Yvon Cazaux ,  Benoit Giffard

IPC: H01L27/146 ,  H04N5/374

CPC classification number: G01S7/4863 ,  G01S7/4914 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14625 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14683 ,  H04N5/374

Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.

公开(公告)号：US20170192090A1

公开(公告)日：2017-07-06

申请号：US15387883

申请日：2016-12-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Francois Roy ,  Marie Guillon ,  Yvon Cazaux ,  Boris Rodrigues ,  Alexis Rochas

IPC: G01S7/486 ,  H01L27/146

CPC classification number: G01S7/4863 ,  G01S7/4914 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14625 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14683 ,  H04N5/374

Abstract: A time-of-flight detection pixel includes a photosensitive area including a first doped layer and a charge collection area extending in the first doped layer. At least two charge storage areas extend from the charge collection area, each including a first well more heavily doped than the charge collection area and separated from the charge collection area by a first portion of the first doped layer which is coated with a gate. Each charge storage area is laterally delimited by two insulated conductive electrodes, extending parallel to each other and facing each other. A second heavily doped layer of opposite conductivity coats the pixel except for at each portion of the first doped layer coated with the gate.

公开(公告)号：US11978756B2

公开(公告)日：2024-05-07

申请号：US17128608

申请日：2020-12-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Sonarith Chhun

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1464

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

公开(公告)号：US11961868B2

公开(公告)日：2024-04-16

申请号：US18198384

申请日：2023-05-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14603 ,  H01L27/14616

Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.

公开(公告)号：US11901381B2

公开(公告)日：2024-02-13

申请号：US16925248

申请日：2020-07-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Andrej Suler

IPC: H01L27/146

CPC classification number: H01L27/14614 ,  H01L27/1464 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L27/14689

Abstract: The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.

公开(公告)号：US11676985B2

公开(公告)日：2023-06-13

申请号：US17122394

申请日：2020-12-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14603 ,  H01L27/14616

Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.

公开(公告)号：US10199409B2

公开(公告)日：2019-02-05

申请号：US15852519

申请日：2017-12-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146 ,  H01L21/822 ,  H01L21/768 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234

Abstract: A semiconductor device includes a first semiconductor substrate with a first transistor therein. The first transistor includes a first source-drain formed by a doped region in the first semiconductor substrate. An intermediary insulating layer is formed on and above the first semiconductor substrate. A second semiconductor substrate is formed on and above the intermediary insulating layer. A second transistor is formed in the second semiconductor substrate, and includes a second source-drain formed by a doped region in the second semiconductor substrate. A trench is formed in the second semiconductor substrate and in contact with the doped region for the second semiconductor substrate. The trench has a thickness equal to that of the second semiconductor substrate. Metal wiring extends from a contact with the doped region for the first source-drain, through the intermediary insulating layer and the trench, to make electrical contact with the doped region for the second source-drain.

公开(公告)号：US20180122846A1

公开(公告)日：2018-05-03

申请号：US15852519

申请日：2017-12-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146 ,  H01L21/822 ,  H01L27/06 ,  H01L27/11 ,  H01L21/768

CPC classification number: H01L27/14609 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823475 ,  H01L27/0688 ,  H01L27/1108 ,  H01L27/14603 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469

Abstract: A semiconductor device includes a first semiconductor substrate with a first transistor therein. The first transistor includes a first source-drain formed by a doped region in the first semiconductor substrate. An intermediary insulating layer is formed on and above the first semiconductor substrate. A second semiconductor substrate is formed on and above the intermediary insulating layer. A second transistor is formed in the second semiconductor substrate, and includes a second source-drain formed by a doped region in the second semiconductor substrate. A trench is formed in the second semiconductor substrate and in contact with the doped region for the second semiconductor substrate. The trench has a thickness equal to that of the second semiconductor substrate. Metal wiring extends from a contact with the doped region for the first source-drain, through the intermediary insulating layer and the trench, to make electrical contact with the doped region for the second source-drain.

公开(公告)号：US20180006075A1

公开(公告)日：2018-01-04

申请号：US15703251

申请日：2017-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14603 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14638 ,  H01L27/14689

Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.