公开(公告)号：US20230387297A1

公开(公告)日：2023-11-30

申请号：US18151021

申请日：2023-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Heun Lee ,  Yong Seok Kim ,  Hyun Cheol Kim ,  Dae Won Ha

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L29/516 ,  H01L29/401 ,  H01L29/6684

Abstract: A semiconductor device including a ferroelectric field effect transistor (FeFET) and a method for fabricating the same are provided. The semiconductor device includes a substrate, a gate electrode film including a metal element, on the substrate, a gate insulating film including a ferroelectric material between the substrate and the gate electrode film, and a buffer oxide film including an oxide of a semiconductor material between the gate insulating film and the gate electrode film, the buffer oxide film being in contact with the gate insulating film.

公开(公告)号：US11798850B2

公开(公告)日：2023-10-24

申请号：US17398623

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi Chan Jun ,  Chang Hwa Kim ,  Dae Won Ha

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L23/522 ,  H01L21/8238

CPC classification number: H01L21/823475 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823814 ,  H01L21/823878

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

公开(公告)号：US20220415931A1

公开(公告)日：2022-12-29

申请号：US17693883

申请日：2022-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Il Park ,  Jae Hyun Park ,  Do Young Choi ,  Yoshinao Harada ,  Dae Won Ha

IPC: H01L27/12 ,  H01L21/822

Abstract: A semiconductor device comprises a substrate, a first active pattern on the substrate and extending in a first direction, a second active pattern extending in the first direction spaced apart from the substrate, a gate electrode extending in a second direction surrounding the first and second active patterns, and a high dielectric film between the first and second active patterns and the gate electrode. The gate electrode includes first and second work function adjusting films surrounding the high dielectric film on the first and second active patterns, and a filling conductive film surrounding the first and second work function adjusting films. The first and second work function adjusting films include first and second work function conductive films, each of which includes a first metal film. A thickness of the first metal film of the first work function conductive film is greater than that of the second work function conductive film.

公开(公告)号：US20220415906A1

公开(公告)日：2022-12-29

申请号：US17577120

申请日：2022-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Il Park ,  Jae Hyun Park ,  Min Gyu Kim ,  Do Young Choi ,  Dae Won Ha

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor memory device and a method for manufacturing the same. The semiconductor memory device may include a substrate, a first lower wire pattern and a first upper wire pattern stacked on the substrate, and spaced apart from each other; a second lower wire pattern and a second upper wire pattern stacked on the substrate, spaced apart from each other, and spaced apart from the first lower and upper wire patterns; a first gate line surrounding the first lower wire pattern and the first upper wire pattern; a second gate line surrounding the second lower wire pattern and the second upper wire pattern and spaced apart from the first gate line; a first lower source/drain area; a first upper source/drain area; and a first overlapping contact that electrically connects the first lower source/drain area, the first upper source/drain area and the second gate line to each other.

公开(公告)号：US11211497B2

公开(公告)日：2021-12-28

申请号：US16848145

申请日：2020-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Gun You ,  Dong Hyun Kim ,  Byoung-Gi Kim ,  Yun Suk Nam ,  Yeong Min Jeon ,  Sung Chui Park ,  Dae Won Ha

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L23/532 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165

Abstract: A semiconductor device includes first and second fin patterns on a substrate and extending apart from each other, a field insulating film on the substrate and surrounding parts of the first and second fin patterns, a first gate structure on the first fin pattern and intersecting the first fin pattern, a second gate structure on the second fin pattern and intersecting the second fin pattern, and a separating structure protruding from a top surface of the field insulating film and separating the first and second gate structures, the field insulating film and the separating structure including a same insulating material.

公开(公告)号：US11195952B2

公开(公告)日：2021-12-07

申请号：US16402292

申请日：2019-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min Kim ,  Hyo Jin Kim ,  Dae Won Ha

IPC: H01L29/78 ,  H01L21/762

Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure including a stress structure and a semiconductor region that are sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. Moreover, the stress structure includes an oxide.

公开(公告)号：US10937887B2

公开(公告)日：2021-03-02

申请号：US16425337

申请日：2019-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guk Il An ,  Keun Hwi Cho ,  Dae Won Ha ,  Seung Seok Ha

IPC: H01L29/51 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L49/02

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

公开(公告)号：US20190057907A1

公开(公告)日：2019-02-21

申请号：US16169326

申请日：2018-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HWI CHAN JUN ,  Chang Hwa Kim ,  Dae Won Ha

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L23/522 ,  H01L27/088

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.