公开(公告)号：US20180113621A1

公开(公告)日：2018-04-26

申请号：US15847916

申请日：2017-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongzhong ZHENG ,  SUHAS ,  Chaohong HU

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0673 ,  G06F13/16

Abstract: An embodiment includes a module, comprising: a memory bus interface; circuitry; and a controller coupled to the memory bus interface and the circuitry, and configured to: collect meta-data associated with the circuitry; and enable access to the meta-data in response to a memory access received through the memory bus interface.

公开(公告)号：US20160307619A1

公开(公告)日：2016-10-20

申请号：US14850938

申请日：2015-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien CHANG ,  Krishna MALLADI ,  Dimin NIU ,  Hongzhong ZHENG

IPC: G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/40615 ,  G11C5/04 ,  G11C5/14 ,  G11C11/40618 ,  G11C11/4076

Abstract: A dynamic Random Access Memory (DRAM) module (105) is disclosed. The DRAM module (105) can includes a plurality of banks (205-1, 205-2, 205-3, 205-4) to store data and a refresh engine (115) that can be used to refresh one of the plurality of banks (205-1, 205-2, 205-3, 205-4). The DRAM module (105) can also include a Smart Refresh Component (305) that can advise the refresh engine (115) which bank to refresh using an out-of-order per-bank refresh. The Smart Refresh Component (305) can use a logic (415) to identify a farthest bank in the pending transactions in the transaction queue (430) at the time of refresh.

Abstract translation: 公开了一种动态随机存取存储器（DRAM）模块（105）。 DRAM模块（105）可以包括用于存储数据的多个存储体（205-1,205-2,205-3,205-4）和可用于刷新多个存储数据中的一个的刷新引擎（115） 银行（205-1,205-2,205-3,205-4）。 DRAM模块（105）还可以包括智能刷新组件（305），该智能刷新组件可以通过使用每次刷新无序刷新哪个存储体来刷新刷新引擎（115）。 在刷新时，智能刷新组件（305）可以使用逻辑（415）来识别事务队列（430）中的待处理事务中的最远存储体。

公开(公告)号：US20160267011A1

公开(公告)日：2016-09-15

申请号：US14732654

申请日：2015-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0877 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/16 ,  G06F2212/60 ,  G06F2212/7203

Abstract: A Solid State Drive (SSD) is disclosed. The SSD can include a host interface logic, a data input buffer, a data output buffer, and a buffer manager to manage the data input buffer and data output buffer. A re-order logic can advise the buffer manager about which data should be returned to the host computer from the data output buffer.

Abstract translation: 公开了固态硬盘（SSD）。 SSD可以包括主机接口逻辑，数据输入缓冲器，数据输出缓冲器和缓冲器管理器，以管理数据输入缓冲器和数据输出缓冲器。 重新排序逻辑可以建议缓冲管理器应该从数据输出缓冲区向主计算机返回哪些数据。

公开(公告)号：US20160266975A1

公开(公告)日：2016-09-15

申请号：US14863446

申请日：2015-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chaohong HU ,  Hongzhong ZHENG ,  Dimin NIU

IPC: G06F11/10 ,  G06F12/10 ,  G06F3/06

CPC classification number: G06F12/1009 ,  G06F11/1048 ,  G06F12/0246 ,  G06F12/0607 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/65 ,  G06F2212/7201

Abstract: An embodiment includes a system, comprising: an Error Correcting Code (ECC) memory comprising a plurality of memory locations, each memory location corresponding to a device address of the ECC memory; a system management bus (SMB); a baseboard management controller (BMC) coupled to the ECC memory through the SMB; and an operating system comprising a driver module coupled to the BMC through the SMB, the driver module being configured to receive through the Memory device address information associated with the ECC memory and to convert the device address information into physical address information independent of an ECC memory controller.

Abstract translation: 一个实施例包括一种系统，包括：纠错码（ECC）存储器，包括多个存储器位置，每个存储器位置对应于ECC存储器的设备地址; 系统管理总线（SMB）; 通过SMB耦合到ECC存储器的基板管理控制器（BMC）; 以及操作系统，其包括通过所述SMB耦合到所述BMC的驱动器模块，所述驱动器模块被配置为通过所述存储器设备接收与所述ECC存储器相关联的地址信息，并将所述设备地址信息转换为独立于ECC存储器的物理地址信息 控制器。

公开(公告)号：US20250077370A1

公开(公告)日：2025-03-06

申请号：US18953042

申请日：2024-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Krishna MALLADI ,  Hongzhong ZHENG

IPC: G06F11/20 ,  G06F3/06

Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.

公开(公告)号：US20230229555A1

公开(公告)日：2023-07-20

申请号：US18127329

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Hyun-Joong KIM ,  Won-hyung SONG ,  Jangseok CHOI

IPC: G06F11/10 ,  G11C5/04 ,  G11C29/42 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C5/04 ,  G11C29/42 ,  G11C29/52

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

公开(公告)号：US20230087747A1

公开(公告)日：2023-03-23

申请号：US18070328

申请日：2022-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG

IPC: G06F12/0879 ,  G11C11/417

Abstract: A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.

公开(公告)号：US20220414030A1

公开(公告)日：2022-12-29

申请号：US17901846

申请日：2022-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Dimin NIU ,  Hongzhong ZHENG

IPC: G06F13/16 ,  G06F12/06

Abstract: A high-bandwidth memory (HBM) includes a memory and a controller. The controller receives a data write request from a processor external to the HBM and the controller stores an entry in the memory indicating at least one address of data of the data write request and generates an indication that a data bus is available for an operation during a cycle time of the data write request based on the data write request comprising sparse data or data-value similarity. Sparse data includes a predetermined percentage of data values equal to zero, and data-value similarity includes a predetermined amount of spatial value locality of the data values. The predetermined percentage of data values equal to zero of sparse data and the predetermined amount of spatial value locality of the special-value pattern are both based on a predetermined data granularity.

公开(公告)号：US20220138132A1

公开(公告)日：2022-05-05

申请号：US17577370

申请日：2022-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG

IPC: G06F13/28 ,  G06F9/445 ,  G06F9/48

Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

公开(公告)号：US20200065017A1

公开(公告)日：2020-02-27

申请号：US16180003

申请日：2018-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyan JIANG ,  Qiang PENG ,  Hongzhong ZHENG

IPC: G06F3/06

Abstract: A memory system provides deduplication of user data in the physical memory space of the system for user data that is duplicated in the virtual memory space of a host system. A transaction manager (TM) uses a transaction table to maintain data coherency and data concurrency for the virtual memory space. A write data engine manager (WDEM) uses an outstanding bucket number and command queues to maintain data coherency and data concurrency for the physical memory space. The WDEM receives data write requests from the TM and sends a corresponding write command to a selected command queue. A write data engine responds to a write command in a command queue by storing the data in an overflow memory region if the data is not duplicated in the virtual memory space, or by incrementing a reference counter for the data if the data is duplicated in the virtual memory space.