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    COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE MEMORY
    7.
    发明申请
    COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE MEMORY 审中-公开

    公开(公告)号：US20200218447A1

    公开(公告)日：2020-07-09

    申请号：US16819032

    申请日：2020-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

    IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

    Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

    SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF
    8.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20240177750A1

    公开(公告)日：2024-05-30

    申请号：US18144531

    申请日：2023-05-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byoungkon JO ,  Gyesik OH ,  Wangyong IM ,  Duk Sung KIM ,  Jangseok CHOI

    IPC: G11C7/10 ,  G11C5/06

    CPC classification number: G11C7/1096 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/1093

    Abstract: A semiconductor memory device, includes, a cell array including a plurality of memory banks, a command decoder configured to decode a read/write command, a read command, and a write command that are input from outside of the semiconductor memory devide, an address decoder receiving a read address and a write address, an input receiver configured to transmit write data input through a write data pad to a global input/output driver of a memory bank corresponding to the write address, and an output driver configured to transmit read data output from an input/output sense amplifier of a memory bank corresponding to the read address to a read data pad, wherein the write data is input via the write data pad in a single data rate method and transmitted to the global input/output driver without deserialization processing, and the read data is transmitted from the input/output sense amplifier to the read data pad without serialization processing. In some embodiments, the semiconductor memory device is electrically and physically coupled to a central processing unit by hybrid copper bonding.

    COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE MEMORY
    9.
    发明申请
    COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE MEMORY 有权

    公开(公告)号：US20220229551A1

    公开(公告)日：2022-07-21

    申请号：US17713228

    申请日：2022-04-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

    IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

    Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

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