公开(公告)号：US11380687B2

公开(公告)日：2022-07-05

申请号：US17126166

申请日：2020-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Mo Park ,  Ju Youn Kim ,  Hyung Joo Na ,  Sang Min Yoo ,  Eui Chui Hwang

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a substrate including first and second regions, first active fins extending in a first direction on the first region, second active fins extending parallel to the first active fins on the second region, and single diffusion break regions between two first active fins. Single diffusion break regions may be spaced apart from each other in the first direction. The semiconductor devices may also include a lower diffusion break region between two second active fins and extending in a second direction that is different from the first direction and upper diffusion break regions on the lower diffusion break region. The upper diffusion break regions may be spaced apart from each other in the first direction, and each of the upper diffusion break regions may overlap the lower diffusion break region.

公开(公告)号：US11355492B2

公开(公告)日：2022-06-07

申请号：US16117065

申请日：2018-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn Kim ,  Gi Gwan Park

IPC: H01L27/088 ,  H01L29/78 ,  H01L49/02 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device including a substrate with a first region and a second region and first and second transistors in the first and second regions, respectively. The first transistor includes a first gate insulating layer on the substrate, a first etch-stop layer, and a first work function layer on the first etch-stop layer. The second transistor includes a second gate insulating layer on the substrate, a second etch-stop layer, and a second work function layer on the second etch-stop layer. At least one of the first and second work function layers is chamfered.

公开(公告)号：US20210210619A1

公开(公告)日：2021-07-08

申请号：US17208186

申请日：2021-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Youn Kim ,  Se Ki Hong

IPC: H01L29/66 ,  H01L27/108 ,  H01L21/28 ,  H01L29/49 ,  H01L27/11

Abstract: A semiconductor device includes a substrate with first and second areas, a first trench in the first area, and first and second PMOS transistors in the first area and the second area, respectively. The first transistor includes a first gate insulating layer, a first TiN layer on and contacting the first gate insulating layer, and a first gate electrode on and contacting the first TiN layer. The second transistor includes a second gate insulating layer, a second TiN layer on and contacting the second gate insulating layer, and a first TiAlC layer on and contacting the second TiN layer. The first gate insulating layer, the first TiN layer, and the first gate electrode are within the first trench. The first gate electrode does not include aluminum. A threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

公开(公告)号：US10930509B2

公开(公告)日：2021-02-23

申请号：US15862768

申请日：2018-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Youn Kim

IPC: H01L21/28 ,  H01L21/762 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/78

Abstract: A semiconductor device includes a fin-type pattern on a substrate, a first gate structure being on the fin-type pattern and including first gate spacers and a first gate insulating layer extending along sidewalls of the first gate spacers, a second gate structure being on the fin-type pattern and including second gate spacers and a second gate insulating layer extending along sidewalk of the second gate spacers, a pair of dummy spacers between the first gate structure and the second gate structure, a separation trench being between the pair of dummy spacers and having sidewalls defined by the pair of dummy spacers and the fin-type pattern, a device isolation layer in a portion of the separation trench, and a connection conductive pattern being on the device isolating layer and in the separation trench and contacting the pair of dummy spacers.

公开(公告)号：US10068904B2

公开(公告)日：2018-09-04

申请号：US15422897

申请日：2017-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju Youn Kim ,  Gi Gwan Park

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0924 ,  H01L28/00

Abstract: A semiconductor device includes first and second active regions and a field insulating film contacting between the first and second active regions, and a gate electrode structure traversing the first and second active regions and the field insulating film, wherein the gate electrode structure includes a first portion positioned across the first active region and the field insulating film, a second portion positioned across the second active region and the field insulating film, and a third portion contacting the first and second portions. The gate electrode structure includes a gate electrode having an insertion film traversing the first and second active regions and the field insulating film second active region, and a filling film on the insertion film. A thickness of the gate electrode in the third portion is different from a thickness of the gate electrode in the first portion and the second portion.

公开(公告)号：US20170179284A1

公开(公告)日：2017-06-22

申请号：US15384587

申请日：2016-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju Youn Kim ,  Gi Gwan Park

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/165 ,  H01L29/06 ,  H01L27/092 ,  H01L29/161

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first fin-type pattern in the first region, a second fin-type pattern in the second region, a first gate structure intersecting the first fin-type pattern, the first gate structure including a first gate spacer, a second gate structure intersecting the second fin-type pattern, the second gate structure including a second gate spacer, a first epitaxial pattern formed on opposite sides of the first gate structure, on the first fin-type pattern, the first epitaxial pattern having a first impurity, a second epitaxial pattern formed on opposite sides of the second gate structure, on the second fin-type pattern, the second epitaxial pattern having a second impurity, a first silicon nitride film extending along a sidewall of the first gate spacer, and a first silicon oxide film extending along a sidewall of the first gate spacer.

公开(公告)号：US20140175609A1

公开(公告)日：2014-06-26

申请号：US13725837

申请日：2012-12-21

Applicant: STMicroelectronics, Inc. ,  Samsung Electronics Co., Ltd. ,  GlobalFoundries Inc. ,  International Business Machines Corporation

Inventor： Pietro Montanini ,  Gerald Leake, JR. ,  Brett H. Engel ,  Roderick Mason Miller ,  Ju Youn Kim

IPC: H01L49/02

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L27/0802 ,  H01L29/66545

Abstract: Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both.

Abstract translation: 使用替代金属栅极（RMG）工艺提供了在金属栅极晶体管旁边创建精密多晶硅电阻的机会。 在牺牲多晶硅栅极的形成期间，也可以由相同的多晶硅膜形成精密多晶硅电阻器。 多晶硅电阻器可以稍微凹进，使得在随后用金属栅极替换牺牲栅极时，保护绝缘层可以覆盖电阻器。 使用这种工艺制造的精密多晶硅电阻器的最终结构比为具有金属栅极晶体管的集成电路提供金属电阻器的现有结构更紧凑和更不复杂。 此外，通过用掺杂剂注入多晶硅膜，调节多晶硅膜厚度或两者，可以将精密多晶硅电阻器自由地调谐为具有所需的薄层电阻。