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公开(公告)号:US10910275B2
公开(公告)日:2021-02-02
申请号:US16599313
申请日:2019-10-11
发明人: Gi Gwan Park , Jung Gun You , Ki Il Kim , Sug Hyun Sung , Myung Yoon Um
IPC分类号: H01L21/8238 , H01L29/66 , H01L27/092 , H01L21/762 , H01L21/8234 , H01L29/78 , H01L29/165
摘要: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.
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公开(公告)号:US10128240B2
公开(公告)日:2018-11-13
申请号:US15807012
申请日:2017-11-08
发明人: Sun Ki Min , Sang Koo Kang , Koung Min Ryu , Gi Gwan Park
IPC分类号: H01L29/06 , H01L27/088 , H01L21/311 , H01L21/8234 , H01L23/535 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/78
摘要: A semiconductor device includes a substrate including first to third regions, wherein the third region is positioned in a first direction between the first and second regions, a fin protruding on the substrate and extending in the first direction, first and second gate structures respectively formed on the fin in the first and second regions, first and second spacers formed with spacing apart from each other on the fin in the third region. The first and second spacers are sloped in a direction away from each other, and the first and second spacers and an upper surface of the fin define a plurality of acute angles, the first and second spacers defining a recess, the fin and the first and second spacers defining sidewalls of the recess, and a device isolating film substantially filling the recess.
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公开(公告)号:US10068901B2
公开(公告)日:2018-09-04
申请号:US15413680
申请日:2017-01-24
发明人: Ju Youn Kim , Gi Gwan Park
IPC分类号: H01L29/49 , H01L27/088 , H01L21/8234 , H01L27/11 , H01L29/423 , H01L29/66
摘要: A semiconductor device including a substrate includes a first region and a second region and first and second transistors in the first and second regions, respectively. The first transistor includes a first gate insulating layer on the substrate, a first lower TiN layer on and in contact with the first gate insulating layer, a first etch-stop layer on the first lower TiN layer and a first upper gate electrode on the first etch-stop layer. The second transistor includes a second gate insulating layer on the substrate, a second lower TiN layer on and in contact with the second gate insulating layer, a second etch-stop layer on the second lower TiN layer and a second upper gate electrode on the second etch-stop layer. A thickness of the first lower TiN layer is less than a thickness of the second lower TiN layer.
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公开(公告)号:US20180138174A1
公开(公告)日:2018-05-17
申请号:US15807012
申请日:2017-11-08
发明人: Sun Ki MIN , Sang Koo Kang , Koung Min Ryu , Gi Gwan Park
IPC分类号: H01L27/088 , H01L29/423 , H01L29/06 , H01L29/08 , H01L23/535 , H01L21/8234 , H01L21/311 , H01L29/66 , H01L29/417 , H01L29/78
CPC分类号: H01L27/0886 , H01L21/3086 , H01L21/31111 , H01L21/762 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L21/823481 , H01L23/535 , H01L29/0649 , H01L29/0847 , H01L29/41783 , H01L29/4232 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要: A semiconductor device includes a substrate including first to third regions, wherein the third region is positioned in a first direction between the first and second regions, a fin protruding on the substrate and extending in the first direction, first and second gate structures respectively formed on the fin in the first and second regions, first and second spacers formed with spacing apart from each other on the fin in the third region. The first and second spacers are sloped in a direction away from each other, and the first and second spacers and an upper surface of the fin define a plurality of acute angles, the first and second spacers defining a recess, the fin and the first and second spacers defining sidewalls of the recess, and a device isolating film substantially filling the recess.
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公开(公告)号:US09899416B2
公开(公告)日:2018-02-20
申请号:US15403307
申请日:2017-01-11
发明人: Bo Soon Kim , Hyun Ji Kim , Jeong Yun Lee , Gi Gwan Park , Sang Duk Park , Young Mook Oh , Yong Seok Lee
IPC分类号: H01L27/088 , H01L27/12 , H01L29/06 , H01L29/423 , H01L21/84 , H01L29/49 , H01L29/51 , H01L21/8234 , H01L29/78
CPC分类号: H01L27/1203 , H01L21/823456 , H01L21/823462 , H01L21/823468 , H01L21/84 , H01L21/845 , H01L27/1211 , H01L29/0653 , H01L29/0673 , H01L29/42392 , H01L29/4908 , H01L29/4966 , H01L29/4991 , H01L29/517 , H01L29/66439 , H01L29/7853
摘要: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.
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公开(公告)号:US10332797B2
公开(公告)日:2019-06-25
申请号:US15480605
申请日:2017-04-06
发明人: Yongkuk Jeong , Gi Gwan Park
IPC分类号: H01L21/308 , H01L21/8234 , H01L21/8238
摘要: A method for fabricating a semiconductor device includes forming first gate stacks on a first region of a substrate to be spaced apart by a first distance, forming second gate stacks on a second region of the substrate to be spaced apart by a second distance greater than the first distance, forming a first blocking film along the first gate stacks and the substrate, a thickness of the first blocking film between the first gate stacks being a first thickness, forming a second blocking film along the second gate stacks and the substrate, a thickness of the second blocking film between the second gate stacks being a second thickness different from the first thickness, and removing the first blocking film, the second blocking film, and the substrate to form a first recess between the first gate stacks and a second recess between the second gate stacks.
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公开(公告)号:US10224343B2
公开(公告)日:2019-03-05
申请号:US15869599
申请日:2018-01-12
发明人: Bo Soon Kim , Hyun Ji Kim , Jeong Yun Lee , Gi Gwan Park , Sang Duk Park , Young Mook Oh , Yong Seok Lee
IPC分类号: H01L27/088 , H01L27/12 , H01L29/06 , H01L29/423 , H01L21/84 , H01L29/66 , H01L29/49 , H01L29/51 , H01L21/8234 , H01L29/78
摘要: There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.
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公开(公告)号:US10043903B2
公开(公告)日:2018-08-07
申请号:US15384587
申请日:2016-12-20
发明人: Ju Youn Kim , Gi Gwan Park
IPC分类号: H01L21/02 , H01L29/78 , H01L27/092 , H01L29/08 , H01L21/8238 , H01L29/66 , H01L29/165
摘要: A semiconductor device includes a substrate including a first region and a second region, a first fin-type pattern in the first region, a second fin-type pattern in the second region, a first gate structure intersecting the first fin-type pattern, the first gate structure including a first gate spacer, a second gate structure intersecting the second fin-type pattern, the second gate structure including a second gate spacer, a first epitaxial pattern formed on opposite sides of the first gate structure, on the first fin-type pattern, the first epitaxial pattern having a first impurity, a second epitaxial pattern formed on opposite sides of the second gate structure, on the second fin-type pattern, the second epitaxial pattern having a second impurity, a first silicon nitride film extending along a sidewall of the first gate spacer, and a first silicon oxide film extending along a sidewall of the first gate spacer.
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公开(公告)号:US10008575B2
公开(公告)日:2018-06-26
申请号:US15298746
申请日:2016-10-20
发明人: Dong Chan Suh , Yong Suk Tak , Gi Gwan Park , Mi Seon Park , Moon Seung Yang , Seung Hun Lee , Poren Tang
IPC分类号: H01L29/423 , H01L29/08 , H01L29/66 , H01L29/78 , H01L23/528 , H01L29/06
CPC分类号: H01L29/42376 , H01L23/5283 , H01L29/0673 , H01L29/0847 , H01L29/42364 , H01L29/42392 , H01L29/66439 , H01L29/7831 , H01L29/78696
摘要: A semiconductor device includes at least a first wire pattern, a gate electrode, a semiconductor pattern, a gate insulating layer, and a first spacer. The first wire pattern is on a substrate and isolated from the substrate. The gate electrode surrounds and intersects the first wire pattern. The semiconductor pattern is on both sides of the first wire pattern, and the semiconductor pattern includes a portion which overlaps the first wire pattern. The gate insulating layer is disposed between the gate electrode and the first wire pattern, and the gate insulating layer surrounds the first wire pattern. The first spacer is between the first wire pattern and the substrate, and the first spacer is between the gate insulating layer and the semiconductor pattern.
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公开(公告)号:US11521900B2
公开(公告)日:2022-12-06
申请号:US17134710
申请日:2020-12-28
发明人: Gi Gwan Park , Jung Gun You , Ki Il Kim , Sug Hyun Sung , Myung Yoon Um
IPC分类号: H01L21/8238 , H01L29/66 , H01L29/78 , H01L27/092 , H01L21/762 , H01L21/8234 , H01L29/165
摘要: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.
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