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    Processing logic modeling and execution
    31.
    发明授权
    Processing logic modeling and execution 失效
    处理逻辑建模和执行

    公开(公告)号：US07873939B2

    公开(公告)日：2011-01-18

    申请号：US12126959

    申请日：2008-05-26

    申请人： Zhong Tian ,  Sheng Ye ,  Xin Zhang ,  Jing Li ,  Wei Sun ,  Guan Qun Zhang

    发明人： Zhong Tian ,  Sheng Ye ,  Xin Zhang ,  Jing Li ,  Wei Sun ,  Guan Qun Zhang

    IPC分类号： G06F9/44

    CPC分类号： G06F8/20

    摘要： Provides processing logic modeling and executing methods, systems and apparatus. These facilitate collaboration between business analyst and IT staff for process modeling and maintenance of the consistency between business level design and IT implementation design. A task is decomposed into sub-tasks and is represented by a tree. Annotations to the nodes of the tree are used to represent the relations between the sub-tasks. A processing logic is thus completed. When executing the processing logic, traversing the tree follows according to the annotations.

    摘要翻译： 提供处理逻辑建模和执行方法，系统和设备。 这些促进了业务分析师和IT人员之间的协作，以进行流程建模和维护业务级设计与IT实施设计之间的一致性。 任务被分解为子任务，并由树表示。 用于树的节点的注释用于表示子任务之间的关系。 从而完成处理逻辑。 执行处理逻辑时，根据注释遍历树。

    RECEIVER ARCHITECTURE WITH DIGITALLY GENERATED INTERMEDIATE FREQUENCY
    32.
    发明申请
    RECEIVER ARCHITECTURE WITH DIGITALLY GENERATED INTERMEDIATE FREQUENCY 有权
    具有数字生成中间频率的接收机架构

    公开(公告)号：US20110009080A1

    公开(公告)日：2011-01-13

    申请号：US12831201

    申请日：2010-07-06

    申请人： Kishore Seendripu ,  Raymond Montemayor ,  Sheng Ye ,  Glenn Chang ,  Curtis Ling

    发明人： Kishore Seendripu ,  Raymond Montemayor ,  Sheng Ye ,  Glenn Chang ,  Curtis Ling

    IPC分类号： H03D5/00

    CPC分类号： H04L5/06 ,  H03D3/008 ,  H03D3/009 ,  H03D7/166 ,  H04B1/30

    摘要： A receiver can be configured to include an RF front end that is configured to downconvert a received signal to a baseband signal or a low Intermediate Frequency (IF) signal. The receiver can downconvert the desired signal from an RF frequency in the presence of numerous interference sources to a baseband or low IF signal for filtering and channel selection. The filtered baseband or low IF signal can be converted to a digital representation. The digital representation of the signal can be upconverted in the digital domain to a programmable IF frequency. The digital IF signal can be converted to an analog IF signal that can be processed by legacy hardware.

    摘要翻译： 接收机可以被配置为包括被配置为将接收到的信号下变频为基带信号或低中频（IF）信号的RF前端。 接收机可以在存在多个干扰源的情况下将来自RF频率的期望信号下变频到用于滤波和信道选择的基带或低IF信号。 滤波后的基带或低IF信号可以转换为数字表示。 信号的数字表示可以在数字域中上转换成可编程的中频。 数字IF信号可以转换为可由传统硬件处理的模拟IF信号。

    Non-isolated DC-DC converters with direct primary to load current
    34.
    发明授权
    Non-isolated DC-DC converters with direct primary to load current 有权

    公开(公告)号：US07307857B2

    公开(公告)日：2007-12-11

    申请号：US11504775

    申请日：2006-08-16

    申请人： Yan-Fei Liu ,  Sheng Ye

    发明人： Yan-Fei Liu ,  Sheng Ye

    IPC分类号： H02M3/335

    CPC分类号： H02M3/1584 ,  H02M3/158 ,  H02M3/1588 ,  H02M3/28 ,  H02M3/285 ,  Y02B70/1425 ,  Y02B70/1466

    摘要： DC-DC converters have high side and rectifier circuits, and output capacitor. High side circuit connects between input voltage and output voltage, and has primary winding and auxiliary section that operate transformer properly. Auxiliary may have switches or combination of switches and capacitors. High side circuit converts electrical into magnetic energy through transformer primary, which is then transferred to output through rectifier circuit. It also transfers energy directly to output voltage. Converters have high efficiency, fast dynamic response and high current output. Converters can have large duty cycle and large input voltage and output voltage conversion ratio. High side circuit can be half-bridge, full-bridge or forward converter. Rectifier uses inductors on either side of the secondary, and diodes or synchronous rectifiers, to rectify output voltage. Multi-phase interleaved circuits utilize shared switches to reduce size. High side circuit can utilize resonant tank to decrease switching losses in auxiliary.

    Non-isolated DC-DC converters with direct primary to load current
    35.
    发明申请
    Non-isolated DC-DC converters with direct primary to load current 有权
    具有直接负载电流的非隔离DC-DC转换器

    公开(公告)号：US20070103941A1

    公开(公告)日：2007-05-10

    申请号：US11504775

    申请日：2006-08-16

    申请人： Yan-Fei Liu ,  Sheng Ye

    发明人： Yan-Fei Liu ,  Sheng Ye

    IPC分类号： H02M3/335

    CPC分类号： H02M3/1584 ,  H02M3/158 ,  H02M3/1588 ,  H02M3/28 ,  H02M3/285 ,  Y02B70/1425 ,  Y02B70/1466

    摘要： DC-DC converters have high side and rectifier circuits, and output capacitor. High side circuit connects between input voltage and output voltage, and has primary winding and auxiliary section that operate transformer properly. Auxiliary may have switches or combination of switches and capacitors. High side circuit converts electrical into magnetic energy through transformer primary, which is then transferred to output through rectifier circuit. It also transfers energy directly to output voltage. Converters have high efficiency, fast dynamic response and high current output. Converters can have large duty cycle and large input voltage and output voltage conversion ratio. High side circuit can be half-bridge, full-bridge or forward converter. Rectifier uses inductors on either side of the secondary, and diodes or synchronous rectifiers, to rectify output voltage. Multi-phase interleaved circuits utilize shared switches to reduce size. High side circuit can utilize resonant tank to decrease switching losses in auxiliary.

    摘要翻译： DC-DC转换器具有高边和整流电路以及输出电容。 高侧电路连接输入电压和输出电压，并具有正常工作变压器的初级绕组和辅助部分。 辅助设备可以有开关或开关和电容器的组合。 高侧电路通过变压器初级将电能转换为磁能，然后通过整流电路传输到输出。 它还可以将能量直接传输到输出电压。 转换器效率高，动态响应快，电流输出高。 转换器可以具有较大的占空比和较大的输入电压和输出电压转换比。 高侧电路可以是半桥，全桥或正转换器。 整流器在二次侧和二极管或同步整流器的任一侧使用电感器来整流输出电压。 多相交错电路利用共享交换机来减小大小。 高侧电路可以利用谐振槽来减少辅助开关损耗。

    CMOS phase locked loop with voltage controlled oscillator having realignment to reference and method for the same
    37.
    发明授权
    CMOS phase locked loop with voltage controlled oscillator having realignment to reference and method for the same 有权
    具有压控振荡器的CMOS锁相环具有与参考相重合的方法及其方法

    公开(公告)号：US06683506B2

    公开(公告)日：2004-01-27

    申请号：US10051378

    申请日：2002-01-18

    申请人： Sheng Ye ,  Ian Galton

    发明人： Sheng Ye ,  Ian Galton

    IPC分类号： H03B2700

    CPC分类号： H03L7/18 ,  H03L7/083 ,  H03L7/0995

    摘要： A periodic controlled realignment of the ring oscillator VCO in a phase locked loop is used to effect phase correction in a CMOS phase locked loop. A realignment to a buffered version of the reference signal is conducted periodically, at a time when an edge of the VCO waveform would ideally coincide with an edge in the reference signal. A preferred embodiment CMOS phase locked loop of the invention uses a ring oscillator voltage controlled oscillator. A divide by M circuit is driven by an output of the voltage controlled oscillator. A control voltage circuit accepts a reference signal and a signal from the divide by M circuit, and produces a control voltage proportional to a phase difference between the output of the voltage controlled oscillator and the reference signal to control the voltage controlled oscillator. A realignment circuit responsive to the reference signal provides a realignment signal into the voltage controlled oscillator when an edge in the waveform of the voltage controlled oscillator ideally coincides with an edge of the reference signal.

    摘要翻译： 环路振荡器VCO在锁相环中的周期性受控重新对准被用于在CMOS锁相环中进行相位校正。 在VCO波形的边缘理想地与参考信号中的边沿重合的时刻周期性地进行参考信号的缓冲版本的重新对准。 本发明的优选实施例CMOS锁相环使用环形振荡器压控振荡器。 M电路的除法由压控振荡器的输出驱动。 控制电压电路接受来自M电路的除法的参考信号和信号，并产生与压控振荡器的输出与参考信号之间的相位差成比例的控制电压，以控制压控振荡器。 响应于参考信号的重新对准电路当压控振荡器的波形中的边缘理想地与参考信号的边沿重合时，将调整信号提供给压控振荡器。

    SOUND GENERATING DEVICE AND METHOD FOR MAKING SAME
    38.
    发明申请
    SOUND GENERATING DEVICE AND METHOD FOR MAKING SAME 审中-公开
    声音发生装置及其制造方法

    公开(公告)号：US20170048600A1

    公开(公告)日：2017-02-16

    申请号：US15082304

    申请日：2016-03-28

    申请人： Xiaofeng Pu ,  Qun Xiang ,  Xudong Yan ,  Bin Zhao ,  Sheng Ye

    发明人： Xiaofeng Pu ,  Qun Xiang ,  Xudong Yan ,  Bin Zhao ,  Sheng Ye

    IPC分类号： H04R1/02 ,  H04R1/32

    CPC分类号： H04R1/023 ,  H04R1/2811 ,  H04R31/00 ,  H04R2499/11

    摘要： A sound generating device is provided in the present disclosure. The sound generating device includes a shell providing a receiving cavity, a sound generating body received in the receiving cavity and assembled to the shell, sound absorbing material filled in the receiving cavity, and an isolating member attached on the sound generating body. The sound generating body includes at least one air hole, and the isolating member covers the at least one air hole, the isolating member is configured for isolating the sound absorbing material from entering the sound generating body. The present disclosure further provides a method for making a sound generating device.

    摘要翻译： 本发明提供一种发声装置。 声音发生装置包括提供接收腔的外壳，容纳在接收腔中并组装到外壳上的声音发生体，填充在接收腔中的吸声材料以及附着在发声体上的隔离构件。 发声体包括至少一个气孔，隔离构件覆盖至少一个气孔，该隔离构件用于隔离吸音材料以进入发声体。 本公开还提供了一种用于制造声音产生装置的方法。

    METHOD AND SYSTEM FOR TIME INTERLEAVED ANALOG-TO-DIGITAL CONVERTER TIMING MISMATCH ESTIMATION AND COMPENSATION
    39.
    发明申请
    METHOD AND SYSTEM FOR TIME INTERLEAVED ANALOG-TO-DIGITAL CONVERTER TIMING MISMATCH ESTIMATION AND COMPENSATION 有权
    时间间隔模拟数字转换器时序误差估计与补偿的方法与系统

    公开(公告)号：US20140009318A1

    公开(公告)日：2014-01-09

    申请号：US13936385

    申请日：2013-07-08

    申请人： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumer ,  Sheng Ye ,  Timothy Leo Gallagher

    发明人： Pawandeep Taluja ,  Mingrui Zhu ,  Xuefeng Chen ,  Anand Anandakumer ,  Sheng Ye ,  Timothy Leo Gallagher

    IPC分类号： H03M1/50

    CPC分类号： H03M1/0612 ,  H03M1/1009 ,  H03M1/1038 ,  H03M1/1215 ,  H03M1/50 ,  H04L7/0087 ,  H04L25/08 ,  H04W56/00

    摘要： Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

    摘要翻译： 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 以及通过使用在期望频率带宽内的频率上的去相关算法来估计期望的数字输出信号和阻塞信号之间的复耦合系数来减少由时间交错ADC中的定时偏移产生的阻塞信号。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。